[gcc/aoliva/heads/testbase] (75 commits) strub: skip emutls after strubm errors

[Alexandre Oliva]

The branch 'aoliva/heads/testbase' was updated to point to:

 5a9e8b0cbbc... strub: skip emutls after strubm errors

It previously pointed to:

 cd3c1cfde73... s390: Fix expansion of vec_step

Diff:

Summary of changes (added commits):
-----------------------------------

  5a9e8b0... strub: skip emutls after strubm errors (*)
  dd3b75d... Daily bump. (*)
  d9965fe... c++: decltype of (non-captured variable) [PR83167] (*)
  0bef725... analyzer: avoid taint for (TAINTED % NON_TAINTED) (*)
  08262e7... analyzer: fix ICE on infoleak with poisoned size (*)
  48cb518... [PR112875][LRA]: Fix an assert in lra elimination code (*)
  662a613... c++: Fix parsing [[]][[]]; (*)
  6ddaf06... c++: Unshare folded SAVE_EXPR arguments during cp_fold [PR1 (*)
  2a5a5d5... c++: Add fixed test [PR88848] (*)
  0c018a7... c++: guard more against undiagnosed error_mark_node [PR1126 (*)
  5764825... c++: undiagnosed error_mark_node from cp_build_c_cast [PR11 (*)
  d468718... RISC-V: Add vectorized strcmp and strncmp. (*)
  2664964... RISC-V: Add vectorized strlen. (*)
  8b5cd6c... aarch64: Some tweaks to the early-ra pass (*)
  a2530e4... Revert "arm: vld1q_types_x2 ACLE intrinsics" (*)
  ccc6226... Revert "arm: vld1q_types_x3 ACLE intrinsics" (*)
  b8adb53... Revert "arm: vld1q_types_x4 ACLE intrinsics" (*)
  5449edc... Revert "arm: vst1_types_x2 ACLE intrinsics" (*)
  c1f800c... Revert "arm: vst1_types_x3 ACLE intrinsics" (*)
  bdd0a50... Revert "arm: vst1_types_x4 ACLE intrinsics" (*)
  3783954... Revert "arm: vst1q_types_x2 ACLE intrinsics" (*)
  684bb3b... Revert "arm: vst1q_types_x3 ACLE intrinsics" (*)
  59f77a8... Revert "arm: vst1q_types_x4 ACLE intrinsics" (*)
  f6d303d... Revert "arm: vld1_types_x2 ACLE intrinsics" (*)
  0a80a35... Revert "arm: vld1_types_x3 ACLE intrinsics" (*)
  b176556... Revert "arm: vld1_types_x4 ACLE intrinsics" (*)
  68d4138... libgcov: Call __builtin_fork instead of fork (*)
  d4b6d14... OpenMP/Fortran: Implement omp allocators/allocate for ptr/a (*)
  47575ec... libgcc: Fix config.in (*)
  91d6866... libgcc: aarch64: Add SME unwinder support (*)
  328c17a... libgcc: aarch64: Add SME runtime support (*)
  dbbfb52... libgcc: aarch64: Configure check for __getauxval (*)
  3ebb591... libgcc: aarch64: Configure check for .variant_pcs support (*)
  5e25baa... tree-optimization/112909 - uninit diagnostic with abnormal  (*)
  3b93ce5... Revert "testsuite: require avx_runtime for some tests" (*)
  75f9c2e... LoongArch: Fix ICE and use simplify_gen_subreg instead of g (*)
  40366b8... LoongArch: Fix lsx-vshuf.c and lasx-xvshuf_b.c tests fail o (*)
  22362d0... LoongArch: Vectorized loop unrolling is disable for divf/sq (*)
  9a07bc4... LoongArch: New options -mrecip and -mrecip= with ffast-math (*)
  276c761... LoongArch: Redefine pattern for xvfrecip/vfrecip instructio (*)
  cd2f1d9... LoongArch: Use standard pattern name for xvfrsqrt/vfrsqrt i (*)
  61f1001... LoongArch: Add support for LoongArch V1.1 approximate instr (*)
  63a541a... Shrink out-of-SSA dump (*)
  51b8259... RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_B (*)
  bf3ff05... LoongArch: Add support for xorsign. (*)
  f32e49a... lower-bitint: Avoid merging non-mergeable stmt with cast an (*)
  b5cfbb8... vr-values: Avoid ICEs on large _BitInt cast to floating poi (*)
  8f60f54... haifa-sched: Avoid overflows in extend_h_i_d [PR112411] (*)
  f6cc6eb... LoongArch: Remove the definition of ISA_BASE_LA64V110 from  (*)
  2b2a059... LoongArch: Switch loongarch-def from C to C++ to make it po (*)
  39a1ab9... Add IntegerRange for -param=min-nondebug-insn-uid= and fix  (*)
  642190b... i386: Mark Xeon Phi ISAs as deprecated (*)
  b241d91... RISC-V: Remove redundant check of better_main_loop_than_p i (*)
  2efe3a7... tree-optimization/112774: extend the SCEV CHREC tree with a (*)
  9f7ad5e... [PATCH 1/5][V3][ifcvt] optimize x=c ? (y op z) : y by RISC- (*)
  775aeab... analyzer: fix ICE for 2 bits before the start of base regio (*)
  08f89e5... Daily bump. (*)
  71a5ac6... RISC-V: Support interleave vector with different step seque (*)
  0832cf4... libstdc++: Simplify ranges::to closure objects (*)
  cab0083... libstdc++: Fix misleading typedef name in <format> (*)
  2f512f6... libstdc++: Use <cstdint> instead of <stdint.h> in <bits/ato (*)
  1395c57... libstdc++: Fix recent changes to __glibcxx_assert [PR112882 (*)
  9f0f7d8... aarch64: Add an early RA for strided registers (*)
  656f092... arm: vld1_types_x4 ACLE intrinsics (*)
  8e3ae87... arm: vld1_types_x3 ACLE intrinsics (*)
  8fff3f0... arm: vld1_types_x2 ACLE intrinsics (*)
  4ad77f8... arm: vst1q_types_x4 ACLE intrinsics (*)
  2d58d53... arm: vst1q_types_x3 ACLE intrinsics (*)
  2cd0d02... arm: vst1q_types_x2 ACLE intrinsics (*)
  2f48d84... arm: vst1_types_x4 ACLE intrinsics (*)
  ef07ae6... arm: vst1_types_x3 ACLE intrinsics (*)
  a69a7c7... arm: vst1_types_x2 ACLE intrinsics (*)
  ac827ec... arm: vld1q_types_x4 ACLE intrinsics (*)
  2514a33... arm: vld1q_types_x3 ACLE intrinsics (*)
  a1a0cdf... arm: vld1q_types_x2 ACLE intrinsics (*)

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