[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps

[Philipp Tomsich]

https://gcc.gnu.org/g:84199cd547cc551644acf239e3bde3caf012f94c

commit 84199cd547cc551644acf239e3bde3caf012f94c
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Sun Nov 13 21:50:24 2022 +0100

    RISC-V: Ventana-VT1 supports XVentanaCondOps
    
    gcc/ChangeLog:
    
            * config/riscv/riscv-cores.def (RISCV_CORE): Update the
            Ventana-VT1 definition to include the xventanacondops
            extension.
    
    Commit-changes: 2
    - New in v2.

Diff:
---
 gcc/config/riscv/riscv-cores.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24..9e38e9dc72e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76",      "rv64imafdc", "sifive-7-series")
 RISCV_CORE("sifive-u54",      "rv64imafdc", "sifive-5-series")
 RISCV_CORE("sifive-u74",      "rv64imafdc", "sifive-7-series")
 
-RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei",	"ventana-vt1")
+RISCV_CORE("ventana-vt1",     "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops",	"ventana-vt1")
 
 #undef RISCV_CORE