[gcc/vrull/heads/for-upstream] (18 commits) riscv: Add support for strlen inline expansion

[Philipp Tomsich]

The branch 'vrull/heads/for-upstream' was updated to point to:

 50881951576a... riscv: Add support for strlen inline expansion

It previously pointed to:

 d97e9be78f7a... riscv: Add support for strlen inline expansion

Diff:

!!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST):
-------------------------------------------------------------------

  d97e9be... riscv: Add support for strlen inline expansion
  bc337d7... riscv: Use by-pieces to do overlapping accesses in block_mo
  4232c46... riscv: Move riscv_block_move_loop to separate file
  3bfdd3d... riscv: Enable overlap-by-pieces via tune param
  8dbcea6... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit
  63d9d0e... RISC-V: Handle "(a & twobits) == singlebit" in branches usi
  0533c21... RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
  c4af9ca... RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + add
  78df89a... RISC-V: Zihintpause: add __builtin_riscv_pause
  af343f9... RISC-V: Use .p2align for code-alignment
  373e07c... ifcvt: add if-conversion to conditional-zero instructions
  8960ad4... RISC-V: Ventana-VT1 supports XVentanaCondOps
  a86a5f1... RISC-V: Support immediates in XVentanaCondOps
  ecd722d... RISC-V: Add instruction fusion (for ventana-vt1)
  5e04c5a... RISC-V: Add basic support for the Ventana-VT1 core
  790bdb1... RISC-V: Recognize bexti in negated if-conversion
  3e36588... RISC-V: Recognize sign-extract + and cases for XVentanaCond
  49cf3af... RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>


Summary of changes (added commits):
-----------------------------------

  5088195... riscv: Add support for strlen inline expansion
  a0a82c7... riscv: Use by-pieces to do overlapping accesses in block_mo
  bd76c16... riscv: Move riscv_block_move_loop to separate file
  1ab285c... riscv: Enable overlap-by-pieces via tune param
  1490405... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit
  b09a434... RISC-V: Handle "(a & twobits) == singlebit" in branches usi
  0a90878... RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori
  60e9ac0... RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + add
  11a36c1... RISC-V: Zihintpause: add __builtin_riscv_pause
  4c3df1e... RISC-V: Use .p2align for code-alignment
  7ff40c1... ifcvt: add if-conversion to conditional-zero instructions
  21cbb5b... RISC-V: Ventana-VT1 supports XVentanaCondOps
  eb94818... RISC-V: Support immediates in XVentanaCondOps
  a91f812... RISC-V: Add instruction fusion (for ventana-vt1)
  b984846... RISC-V: Add basic support for the Ventana-VT1 core
  01fd2fc... RISC-V: Recognize bexti in negated if-conversion
  442eed7... RISC-V: Recognize sign-extract + and cases for XVentanaCond
  b80d64e... RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>