[gcc r11-9747] RISC-V: Fix register class subset checks for CLASS_MAX_NREGS

[Kito Cheng]

https://gcc.gnu.org/g:6fccb624f13e94d0d5d0fd5d0ff98060c84626a0

commit r11-9747-g6fccb624f13e94d0d5d0fd5d0ff98060c84626a0
Author: Maciej W. Rozycki <macro@embecosm.com>
Date:   Wed Nov 3 17:04:19 2021 +0000

    RISC-V: Fix register class subset checks for CLASS_MAX_NREGS
    
    Fix the register class subset checks in the determination of the maximum
    number of consecutive registers needed to hold a value of a given mode.
    
    The number depends on whether a register is a general-purpose or a
    floating-point register, so check whether the register class requested
    is a subset (argument 1 to `reg_class_subset_p') rather than superset
    (argument 2) of GR_REGS or FP_REGS class respectively.
    
            gcc/
            * config/riscv/riscv.c (riscv_class_max_nregs): Swap the
            arguments to `reg_class_subset_p'.
    
    (cherry picked from commit a31056e9196daf0a5b0e92d171b5227cc994103b)

Diff:
---
 gcc/config/riscv/riscv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 17cdf705c32..697b82381b2 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -4574,10 +4574,10 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)
 static unsigned char
 riscv_class_max_nregs (reg_class_t rclass, machine_mode mode)
 {
-  if (reg_class_subset_p (FP_REGS, rclass))
+  if (reg_class_subset_p (rclass, FP_REGS))
     return riscv_hard_regno_nregs (FP_REG_FIRST, mode);
 
-  if (reg_class_subset_p (GR_REGS, rclass))
+  if (reg_class_subset_p (rclass, GR_REGS))
     return riscv_hard_regno_nregs (GP_REG_FIRST, mode);
 
   return 0;