[gcc(refs/users/meissner/heads/work080)] revert patch.

Tue Mar 8 03:58:01 GMT 2022

https://gcc.gnu.org/g:489b9a56dc54b039431bbcb08631a483822da3d9

commit 489b9a56dc54b039431bbcb08631a483822da3d9
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Mar 7 22:57:27 2022 -0500

 revert patch.
 
 Optimize multiply/add of DImode extended to TImode.
 
 On power9 and power10 systems, we have instructions that support doing
 64-bit integers converted to 128-bit integers and producing 128-bit
 results. This patch adds support to generate these instructions.
 
 Previously we had define_expands to handle conversion of the 64-bit extend
 to 128-bit and multiply. This patch changes these define_expands to
 define_insn_and_split and then it provides combiner patterns to generate
 thes multiply/add instructions.
 
 To support using this optimization on power9, we extend the sign extend
 DImode to TImode to also run on power9 (added for PR target/104698).
 
 We add support for doing an unsigned DImode to TImode conversion. We need
 these conversions to exist on power9 so that the combiner can properly
 combine the extend, multiply, and add instructions.
 
 2022-03-07 Michael Meissner <meissner@linux.ibm.com>
 
 gcc/
 Revert patch.
 PR target/103109
 * config/rs6000/rs6000.md (su_int32): New code attribute.
 (mul<mode><dmode>3): Convert from define_expand to
 define_insn_and_split.
 (maddld<mode>4): Add generator function.
 (mulditi3_adddi3): New insn.
 (mulditi3_add_const): New insn.
 (mulditi3_adddi3_upper): New insn.
 (addti3): Convert from define_expand to define_insn_and_split.
 (subti3): Likewise.
 * config/rs6000/vsx.md (extendditi2): Allow on power9 systems.
 Add isa attribute for the stuff that needs power10 support.
 (zero_extendditi2): New insn.

Diff:
---
 gcc/config/rs6000/rs6000.md | 166 +++++---------------------------------------
 1 file changed, 17 insertions(+), 149 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index da7367ee642..fdfbc6566a5 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -676,9 +676,6 @@
 		       (float		"")
 		       (unsigned_float	"uns")])
 
-(define_code_attr su_int32 [(sign_extend "s32bit_cint_operand")
-			    (zero_extend "c32bit_cint_operand")])
-
 ; Various instructions that come in SI and DI forms.
 ; A generic w/d attribute, for things like cmpw/cmpd.
 (define_mode_attr wd [(QI    "b")
@@ -3202,16 +3199,13 @@
   "mulhw<u> %0,%1,%2"
   [(set_attr "type" "mul")])
 
-(define_insn_and_split "<u>mul<mode><dmode>3"
-  [(set (match_operand:<DMODE> 0 "gpc_reg_operand" "=&r")
+(define_expand "<u>mul<mode><dmode>3"
+  [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
 	(mult:<DMODE> (any_extend:<DMODE>
-		       (match_operand:GPR 1 "gpc_reg_operand" "r"))
+			(match_operand:GPR 1 "gpc_reg_operand"))
 		      (any_extend:<DMODE>
-		       (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
+			(match_operand:GPR 2 "gpc_reg_operand"))))]
   "!(<MODE>mode == SImode && TARGET_POWERPC64)"
-  "#"
-  "&& 1"
-  [(pc)]
 {
   rtx l = gen_reg_rtx (<MODE>mode);
   rtx h = gen_reg_rtx (<MODE>mode);
@@ -3220,10 +3214,9 @@
   emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
   emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
   DONE;
-}
-  [(set_attr "length" "8")])
+})
 
-(define_insn "maddld<mode>4"
+(define_insn "*maddld<mode>4"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
 	(plus:GPR (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
 			    (match_operand:GPR 2 "gpc_reg_operand" "r"))
@@ -3232,115 +3225,6 @@
   "maddld %0,%1,%2,%3"
   [(set_attr "type" "mul")])
 
-(define_insn_and_split "*<u>mulditi3_<u>adddi3"
-  [(set (match_operand:TI 0 "gpc_reg_operand" "=&r")
-	(plus:TI
-	 (mult:TI
-	  (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
-	  (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
-	 (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r"))))]
-  "TARGET_MADDLD && TARGET_POWERPC64"
-  "#"
-  "&& 1"
-  [(pc)]
-{
-  rtx dest = operands[0];
-  rtx dest_hi = gen_highpart (DImode, dest);
-  rtx dest_lo = gen_lowpart (DImode, dest);
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  rtx op3 = operands[3];
-  rtx tmp_hi, tmp_lo;
-
-  if (can_create_pseudo_p ())
-    {
-      tmp_hi = gen_reg_rtx (DImode);
-      tmp_lo = gen_reg_rtx (DImode);
-    }
-  else
-    {
-      tmp_hi = dest_hi;
-      tmp_lo = dest_lo;
-    }
-
-  emit_insn (gen_<u>mulditi3_<u>adddi3_upper (tmp_hi, op1, op2, op3));
-  emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3));
-
-  if (can_create_pseudo_p ())
-    {
-      emit_move_insn (dest_hi, tmp_hi);
-      emit_move_insn (dest_lo, tmp_lo);
-    }
-  DONE;
-}
-  [(set_attr "length" "8")])
-
-;; Optimize 128-bit multiply with zero/sign extend and adding a constant.  We
-;; force the constant into a register to generate li, maddhd, and maddld,
-;; instead of mulld, mulhd, addic, and addze.  We can't combine this pattern
-;; with the pattern that handles registers, since constants don't have a sign
-;; or zero extend around them.
-(define_insn_and_split "*<u>mulditi3_add_const"
-  [(set (match_operand:TI 0 "gpc_reg_operand" "=&r")
-	(plus:TI
-	 (mult:TI
-	  (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
-	  (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
-	 (match_operand 3 "<su_int32>" "r")))]
-  "TARGET_MADDLD && TARGET_POWERPC64
-"
-  "#"
-  "&& 1"
-  [(pc)]
-{
-  rtx dest = operands[0];
-  rtx dest_hi = gen_highpart (DImode, dest);
-  rtx dest_lo = gen_lowpart (DImode, dest);
-  rtx op1 = operands[1];
-  rtx op2 = operands[2];
-  rtx op3 = force_reg (DImode, operands[3]);
-  rtx tmp_hi, tmp_lo;
-
-  if (can_create_pseudo_p ())
-    {
-      tmp_hi = gen_reg_rtx (DImode);
-      tmp_lo = gen_reg_rtx (DImode);
-    }
-  else
-    {
-      tmp_hi = dest_hi;
-      tmp_lo = dest_lo;
-    }
-
-  emit_insn (gen_<u>mulditi3_<u>adddi3_upper (tmp_hi, op1, op2, op3));
-  emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3));
-
-  if (can_create_pseudo_p ())
-    {
-      emit_move_insn (dest_hi, tmp_hi);
-      emit_move_insn (dest_lo, tmp_lo);
-    }
-  DONE;
-}
-  [(set_attr "length" "8")
-   (set_attr "type" "mul")
-   (set_attr "size" "64")])
-
-(define_insn "<u>mulditi3_<u>adddi3_upper"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-	(truncate:DI
-	 (lshiftrt:TI
-	  (plus:TI
-	   (mult:TI
-	    (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
-	    (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
-	   (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r")))
-	  (const_int 64))))]
-  "TARGET_MADDLD && TARGET_POWERPC64"
-  "maddhd<u> %0,%1,%2,%3"
-  [(set_attr "type" "mul")
-   (set_attr "size" "64")])
-
 (define_insn "udiv<mode>3"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
         (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
@@ -7145,19 +7029,12 @@
 ;; allocator from allocating registers that overlap with the inputs
 ;; (for example, having an input in 7,8 and an output in 6,7).  We
 ;; also allow for the output being the same as one of the inputs.
-;;
-;; Addti3/subti3 are define_insn_and_splits instead of define_expand, to allow
-;; for combine to make things like multiply and add with extend operations.
-
-(define_insn_and_split "addti3"
-  [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r")
-	(plus:TI (match_operand:TI 1 "gpc_reg_operand" "r,0,r")
-		 (match_operand:TI 2 "reg_or_short_operand" "rn,r,0")))
-   (clobber (reg:DI CA_REGNO))]
+
+(define_expand "addti3"
+  [(set (match_operand:TI 0 "gpc_reg_operand")
+	(plus:TI (match_operand:TI 1 "gpc_reg_operand")
+		 (match_operand:TI 2 "reg_or_short_operand")))]
   "TARGET_64BIT"
-  "#"
-  "&& 1"
-  [(pc)]
 {
   rtx lo0 = gen_lowpart (DImode, operands[0]);
   rtx lo1 = gen_lowpart (DImode, operands[1]);
@@ -7174,19 +7051,13 @@
   emit_insn (gen_adddi3_carry (lo0, lo1, lo2));
   emit_insn (gen_adddi3_carry_in (hi0, hi1, hi2));
   DONE;
-}
-  [(set_attr "length" "8")
-   (set_attr "type" "add")
-   (set_attr "size" "128")])
+})
 
-(define_insn_and_split "subti3"
-  [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r")
-	(minus:TI (match_operand:TI 1 "reg_or_short_operand" "rn,0,r")
-		  (match_operand:TI 2 "gpc_reg_operand" "r,r,0")))]
+(define_expand "subti3"
+  [(set (match_operand:TI 0 "gpc_reg_operand")
+	(minus:TI (match_operand:TI 1 "reg_or_short_operand")
+		  (match_operand:TI 2 "gpc_reg_operand")))]
   "TARGET_64BIT"
-  "#"
-  "&& 1"
-  [(pc)]
 {
   rtx lo0 = gen_lowpart (DImode, operands[0]);
   rtx lo1 = gen_lowpart (DImode, operands[1]);
@@ -7203,10 +7074,7 @@
   emit_insn (gen_subfdi3_carry (lo0, lo2, lo1));
   emit_insn (gen_subfdi3_carry_in (hi0, hi2, hi1));
   DONE;
-}
-  [(set_attr "length" "8")
-   (set_attr "type" "add")
-   (set_attr "size" "128")])
+})
 
 ;; 128-bit logical operations expanders
