[gcc r12-6775] aarch64: allow ld1/stq in test output [PR102517]

[Richard Earnshaw]

https://gcc.gnu.org/g:62eb400b51f8a552320a250b3ac0b5d2ebd8927f

commit r12-6775-g62eb400b51f8a552320a250b3ac0b5d2ebd8927f
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Thu Jan 20 15:41:37 2022 +0000

     aarch64: allow ld1/stq in test output [PR102517]
    
    Following the changes to the inline memcpy operations get expanded, we
    now generate ld1/st1 using a 128-bit vector register rather than ldp
    with Q registers.  The behaviour is equivalent, so relax the tests to
    permit either variant.
    
    gcc/testsuite/ChangeLog:
    
            PR target/102517
            * gcc.target/aarch64/cpymem-q-reg_1.c: Allow ld1 and st1 for the
            memcpy expansion.

Diff:
---
 gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c b/gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c
index df5f67e425b..45f3f0ad144 100644
--- a/gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/cpymem-q-reg_1.c
@@ -10,7 +10,7 @@ foo (void)
   __builtin_memcpy (dst, src, N * sizeof (int));
 }
 
-/* { dg-final { scan-assembler {ldp\tq[0-9]*} } } */
+/* { dg-final { scan-assembler {ldp\tq[0-9]*|ld1\t{v[0-9]*\.16b - v[0-9]*\.16b}} } } */
 /* { dg-final { scan-assembler-not {ldp\tx[0-9]*} } } */
-/* { dg-final { scan-assembler {stp\tq[0-9]*} } } */
+/* { dg-final { scan-assembler {stp\tq[0-9]*|st1\t{v[0-9]*\.16b - v[0-9]*\.16b}} } } */
 /* { dg-final { scan-assembler-not {stp\tx[0-9]*} } } */