[gcc(refs/vendors/ARM/heads/morello)] Minor fix to exclude fake-capability from using the purecap exception table layout

[Matthew Malcomson]

https://gcc.gnu.org/g:c5acd3ba7b94df2ca423f33258af10431b0f65a5

commit c5acd3ba7b94df2ca423f33258af10431b0f65a5
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Tue Feb 8 11:15:40 2022 +0000

    Minor fix to exclude fake-capability from using the purecap exception table layout
    
    During recent C++ work it was found that the "fake-capability" ABI
    was picking up recent changes to the exception table landing pad
    layout, that were intended only for Purecap. That is wrong, because
    "fake-capability" is intended to always output standard A64 AAPCS
    code, with the notion of capabilities existing only within the compiler.
    
    This patch makes use of the `capabilities_in_hardware` target hook
    to exclude this behaviour.

Diff:
---
 gcc/except.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/gcc/except.c b/gcc/except.c
index 03d7d529958..e8a53d3a755 100644
--- a/gcc/except.c
+++ b/gcc/except.c
@@ -2897,9 +2897,15 @@ dw2_output_call_site_table (int cs_format, int section)
 					"region %d start", i);
 	  dw2_asm_output_delta_uleb128 (reg_end_lab, reg_start_lab,
 					"length");
-	  /* For capability targets we use an alternate schema for the call
-	     site table.  */
+
+	  /* For pure-capability targets we can't use constant integer values,
+	     instead we need to use valid capabilities. This is done with a
+	     capability-aware table layout that and constant addres
+	     capabilities that get placed in the RELRO section. The table
+	     entries then contain a capability marker value and an offset from
+	     the table entry address to the capability in RELRO.  */
 	  if (targetm.capability_mode().exists()
+	      && targetm.capabilities_in_hardware()
 	      && targetm.capability_mode().require() == Pmode
 	      && cs->landing_pad)
 	    {