[gcc(refs/users/clyon/heads/mve-autovec)] arm: Add tests for PR target/101325

[Christophe Lyon]

https://gcc.gnu.org/g:2f3d15e94a694bbf5141a0e079639ee519e688bc

commit 2f3d15e94a694bbf5141a0e079639ee519e688bc
Author: Christophe Lyon <christophe.lyon@foss.st.com>
Date:   Wed Oct 20 15:27:54 2021 +0000

    arm: Add tests for PR target/101325
    
    These tests are derived from the one provided in the PR: there is a
    compile-only test because I did not have access to anything that could
    execute MVE code until recently.
    I have been able to add an executable test since QEMU supports MVE.
    
    Instead of adding arm_v8_1m_mve_hw, I update arm_mve_hw so that it
    uses add_options_for_arm_v8_1m_mve_fp, like arm_neon_hw does.  This
    ensures arm_mve_hw passes even if the toolchain does not generate MVE
    code by default.
    
    2022-01-13  Christophe Lyon  <christophe.lyon@foss.st.com>
    
            gcc/testsuite/
            PR target/101325
            * gcc.target/arm/simd/pr101325.c: New.
            * gcc.target/arm/simd/pr101325-2.c: New.
            * lib/target-supports.exp (check_effective_target_arm_mve_hw): Use
            add_options_for_arm_v8_1m_mve_fp.

Diff:
---
 gcc/testsuite/gcc.target/arm/simd/pr101325-2.c | 19 +++++++++++++++++++
 gcc/testsuite/gcc.target/arm/simd/pr101325.c   | 14 ++++++++++++++
 gcc/testsuite/lib/target-supports.exp          |  3 ++-
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/arm/simd/pr101325-2.c b/gcc/testsuite/gcc.target/arm/simd/pr101325-2.c
new file mode 100644
index 00000000000..355f6473a00
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/pr101325-2.c
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O3" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include <arm_mve.h>
+
+
+__attribute((noipa))
+unsigned foo(int8x16_t v, int8x16_t w)
+{
+  return vcmpeqq (v, w);
+}
+
+int main(void)
+{
+  if (foo (vdupq_n_s8(0), vdupq_n_s8(0)) != 0xffffU)
+    __builtin_abort ();
+}
diff --git a/gcc/testsuite/gcc.target/arm/simd/pr101325.c b/gcc/testsuite/gcc.target/arm/simd/pr101325.c
new file mode 100644
index 00000000000..4cb2513da87
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/pr101325.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <arm_mve.h>
+
+unsigned foo(int8x16_t v, int8x16_t w)
+{
+  return vcmpeqq (v, w);
+}
+/* { dg-final { scan-assembler {\tvcmp.i8  eq} } } */
+/* { dg-final { scan-assembler {\tvmrs\tr[0-9]+, P0} } } */
+/* { dg-final { scan-assembler {\tuxth} } } */
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index b4bf2e6b495..0fe1e1e077a 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -5037,6 +5037,7 @@ proc check_effective_target_arm_cmse_hw { } {
 	}
     } "-mcmse"]
 }
+
 # Return 1 if the target supports executing MVE instructions, 0
 # otherwise.
 
@@ -5052,7 +5053,7 @@ proc check_effective_target_arm_mve_hw {} {
 	       : "0" (a), "r" (b));
 	  return (a != 2);
 	}
-    } ""]
+    } [add_options_for_arm_v8_1m_mve_fp ""]]
 }
 
 # Return 1 if this is an ARM target where ARMv8-M Security Extensions with