[gcc(refs/users/meissner/heads/work098)] Revert patches.
Michael Meissner
meissner@gcc.gnu.org
Wed Aug 17 23:20:23 GMT 2022
https://gcc.gnu.org/g:e87570f87ca9993dac140861e2d774755e16212a
commit e87570f87ca9993dac140861e2d774755e16212a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Aug 17 19:16:21 2022 -0400
Revert patches.
2022-08-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Always use the
_Float128 type for __float128. Don't use the long double type.
* config/rs6000/rs6000.cc (rs6000_libgcc_floating_mode_supported_p):
Always use KFmode for Float128 mode.
(rs6000_floatn_mode): Likewise.
(rs6000_c_mode_for_suffix): Likewise.
2022-08-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Update
switching from KFmode/IFmode built-in functions to TFmode built-in
functions.
2022-08-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/predicates.md (ieee128_operand): New predicate.
* config/rs6000/rs6000.md (trunc<mode>sf2_hw): Use ieee128_operand.
(round<mode>2): Likewise.
(add<mode>3_odd): Likewise.
(sub<mode>3_odd): Likewise.
(mul<mode>3_odd): Likewise.
(div<mode>3_odd): Likewise.
(sqrt<mode>2_odd): Likewise.
(fma<mode>4_odd): Likewise.
(fms<mode>4_odd): Likewise.
(nfma<mode>4_odd): Likewise.
(nfms<mode>4_odd): Likewise.
(trunc<mode>df2_odd): Likewise.
* config/rs6000/vsx.md (xsxexpqp_<mode>): Likewise.
(xsxsigqp_<mode>): Likewise.
(xsiexpqpf_<mode>): Likewise.
(xscmpexpqp_<code>_<mode): Likewise.
(xscmpexpqp_<code>_<mode>): Likewise.
(xststdcqp_<mode>): Likewise.
(xststdcnegqp_<mode>): Likewise.
(xststdcqp_<mode>): Likewise.
2022-08-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/rs6000.md (IFKF): Delete.
(IFKF_reg): Delete.
(extendkfif2): New define_expand.
(trunckfif2): New define_expand.
(extend<mode>tf2_internal): Split into extendiftf2_internal and
extendkftf2_internal. Update the insns to use the correct insn type and
length attributes based on whether the move uses IEEE 128-bit floating
point or IBM 128-bit floating point type.
(extendiftf2_internal): Likewise.
(extendkftf2_internal): Likewise.
(extendtf<mode>2_internal): Split into extendtfif2_internal and
extendtfkf2_internal. Update the insns to use the correct insn type and
length attributes based on whether the move uses IEEE 128-bit floating e
point or IBM 128-bit floating point type.
(extendtfif2_internal): Likewise.
(extendtfkf2_internal): Likewise.
2022-08-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/rs6000-c.cc (rs6000_cpu_cpp_builtins): Set
building_libgcc.
* config/rs6000/rs6000.cc (create_complex_muldiv): Delete.
(init_float128_ieee): Delete code to switch complex multiply and divide
for long double.
(complex_multiply_builtin_code): New helper function.
(complex_divide_builtin_code): Likewise.
(rs6000_mangle_decl_assembler_name): Add support for mangling the name
of complex 128-bit multiply and divide built-in functions.
* config/rs6000/rs6000.opt (building_libgcc): New target variable.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/divic3-1.c: New test.
* gcc.target/powerpc/divic3-2.c: Likewise.
* gcc.target/powerpc/mulic3-1.c: Likewise.
* gcc.target/powerpc/mulic3-2.c: Likewise.
2022-08-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/rs6000.cc (rs6000_c_mode_for_suffix): Allow 'w' or 'W'
for __ibm128 constants.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/ibm128-suffix.c: New test.
2022-08-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/rs6000-builtins.cc (rs6000_init_builtins): Enable using
the__ibm128 keyword on systems that either use the 128-bit IBM long
double format for long double or support IEEE 128-bit.
* config/rs6000/rs6000.cc (rs6000_init_libfuncs): Create IBM 128-bit
floating point support functions on systems that support the __ibm128
keyword.
(rs6000_scalar_mode_supported_p): Likewise.
* config/rs6000/rs6000.h (TARGET_IBM128): New macro.
* config/rs6000/rs6000.md (@extenddf<mode>2_fprs): Allow IFmode to be
converted even if long double is not 128-bits.
(extenddf<mode>2_vsx): Likewise.
(extendiftf2):Allow conversion on systems that support the __ibm128
keyword.
(extendtfif2): Likewise.
(trunciftf2): Likewise.
(trunctfif2): Likewise.
2022-08-17 Michael Meissner <meissner@linux.ibm.com>
gcc/
* ChangeLog.meissner: Update.
Diff:
---
gcc/ChangeLog.meissner | 244 +----------------------
gcc/config/rs6000/predicates.md | 25 ---
gcc/config/rs6000/rs6000-builtin.cc | 75 +++----
gcc/config/rs6000/rs6000-c.cc | 8 -
gcc/config/rs6000/rs6000.cc | 186 +++++++++--------
gcc/config/rs6000/rs6000.h | 8 +-
gcc/config/rs6000/rs6000.md | 157 +++++----------
gcc/config/rs6000/rs6000.opt | 4 -
gcc/config/rs6000/vsx.md | 20 +-
gcc/testsuite/gcc.target/powerpc/divic3-1.c | 18 --
gcc/testsuite/gcc.target/powerpc/divic3-2.c | 17 --
gcc/testsuite/gcc.target/powerpc/ibm128-suffix.c | 13 --
gcc/testsuite/gcc.target/powerpc/mulic3-1.c | 18 --
gcc/testsuite/gcc.target/powerpc/mulic3-2.c | 17 --
14 files changed, 203 insertions(+), 607 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 10503baba94..f27c6009d73 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,246 +1,20 @@
-==================== work098, patch #9
+==================== work098, patch #9 was reverted.
-Make __float128 use the _Float128 type.
+==================== work098, patch #8 was reverted.
-2022-08-17 Michael Meissner <meissner@linux.ibm.com>
+==================== work098, patch #7 was reverted.
-gcc/
+==================== work098, patch #6 was reverted.
- * config/rs6000/rs6000-builtin.cc (rs6000_init_builtins): Always use the
- _Float128 type for __float128. Don't use the long double type.
- * config/rs6000/rs6000.cc (rs6000_libgcc_floating_mode_supported_p):
- Always use KFmode for Float128 mode.
- (rs6000_floatn_mode): Likewise.
- (rs6000_c_mode_for_suffix): Likewise.
+==================== work098, patch #5 was reverted.
-==================== work098, patch #8
+==================== work098, patch #4 was reverted.
-Update switching between equivalent 128-bit FP in builtins
+==================== work098, patch #3 was reverted.
-This patch looks to see if the caller function was passed TFmode. If it was
-passed TFmode and the built-in function uses KFmode, switch the built-in
-function to the equivalent TFmode built-in. Similarly, if it was passed TFmode
-and the built-in functions uses IFmode, switch the built-in function to the
-equivalent TFmode built-in.
+==================== work098, patch #2 was reverted.
-In the past the code would do the conversion based on what 128-bit floating
-point format was used. This patch changes this to look at the arguments. If
-any of the arguments use TFmode instead of KFmode or IFmode, it will do the
-conversion.
-
-2022-08-17 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Update
- switching from KFmode/IFmode built-in functions to TFmode built-in
- functions.
-
-==================== work098, patch #7 was reverted
-
-==================== work098, patch #6
-
-Add ieee128_operand.
-
-Since we have 2 modes for IEEE 128-bit (KFmode and TFmode if long double is IEEE
-128-bit), this patch provides a new predicate (ieee128_operand) that allows
-combining a conversion from one mode to another.
-
-2022-08-17 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/predicates.md (ieee128_operand): New predicate.
- * config/rs6000/rs6000.md (trunc<mode>sf2_hw): Use ieee128_operand.
- (round<mode>2): Likewise.
- (add<mode>3_odd): Likewise.
- (sub<mode>3_odd): Likewise.
- (mul<mode>3_odd): Likewise.
- (div<mode>3_odd): Likewise.
- (sqrt<mode>2_odd): Likewise.
- (fma<mode>4_odd): Likewise.
- (fms<mode>4_odd): Likewise.
- (nfma<mode>4_odd): Likewise.
- (nfms<mode>4_odd): Likewise.
- (trunc<mode>df2_odd): Likewise.
- * config/rs6000/vsx.md (xsxexpqp_<mode>): Likewise.
- (xsxsigqp_<mode>): Likewise.
- (xsiexpqpf_<mode>): Likewise.
- (xscmpexpqp_<code>_<mode): Likewise.
- (xscmpexpqp_<code>_<mode>): Likewise.
- (xststdcqp_<mode>): Likewise.
- (xststdcnegqp_<mode>): Likewise.
- (xststdcqp_<mode>): Likewise.
-
-==================== work098, patch #5
-
-Improve converting between 128-bit modes that use the same format.
-
-This patch improves the insns used for converting between two modes using
-the 128-bit floating point format (i.e. converting between KFmode and TFmode if
--mabi=ieeelongdouble is used, and converting between IFmode and TFmode if
--mabi=ibmlongdouble is used). The new insns have the correct insn type and
-instruction length for the move involved.
-
-2022-08-17 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/rs6000.md (IFKF): Delete.
- (IFKF_reg): Delete.
- (extendkfif2): New define_expand.
- (trunckfif2): New define_expand.
- (extend<mode>tf2_internal): Split into extendiftf2_internal and
- extendkftf2_internal. Update the insns to use the correct insn type and
- length attributes based on whether KFmode or IFmode is used.
- (extendiftf2_internal): Likewise.
- (extendkftf2_internal): Likewise.
- (extendtf<mode>2_internal): Split into extendtfif2_internal and
- extendtfkf2_internal. Update the insns to use the correct insn type and
- length attributes based on whether KFmode or IFmode is used.
- (extendtfif2_internal): Likewise.
- (extendtfkf2_internal): Likewise.
-
-==================== work098, patch #4
-
-Rework 128-bit complex multiply and divide.
-
-This function reworks how the complex multiply and divide built-in functions are
-done. Previously we created built-in declarations for doing long double complex
-multiply and divide when long double is IEEE 128-bit. The old code also did not
-support __ibm128 complex multiply and divide if long double is IEEE 128-bit.
-
-In terms of history, I wrote the original code just as I was starting to test
-GCC on systems where IEEE 128-bit long double was the default. At the time, we
-had not yet started mangling the built-in function names as a way to bridge
-going from a system with 128-bit IBM long double to 128-bin IEEE long double.
-
-The original code depends on there only being two 128-bit types invovled. With
-some of the changes that I plan on making, this assumption will no longer be
-true in the future.
-
-The problem is we cannot create two separate built-in functions that resolve to
-the same name. This is a requirement of add_builtin_function and the C front
-end. That means for the 3 possible modes (IFmode, KFmode, and TFmode), you can
-only use 2 of them.
-
-This code does not create the built-in declaration with the changed name.
-Instead, it uses the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change the name
-before it is written out to the assembler file like it now does for all of the
-other long double built-in functions.
-
-We need to disable using this mapping when we are building libgcc, which is
-creating the multiply and divide functions. The flag that is used when libgcc
-is built (-fbuilding-libcc) is only available in the C/C++ front ends. We need
-to remember that we are building libgcc in the rs6000-c.cc support to be able to
-use this later to decided whether to mangle the decl assembler name or not.
-
-When I wrote these patches, I discovered that __ibm128 complex multiply and
-divide had originally not been supported if long double is IEEE 128-bit as it
-would generate calls to __mulic3 and __divic3. I added tests in the testsuite
-to verify that the correct name (i.e. __multc3 and __divtc3) is used in this
-case.
-
-2022-08-17 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/rs6000-c.cc (rs6000_cpu_cpp_builtins): Set
- building_libgcc.
- * config/rs6000/rs6000.cc (create_complex_muldiv): Delete.
- (init_float128_ieee): Delete code to switch complex multiply and divide
- for long double.
- (complex_multiply_builtin_code): New helper function.
- (complex_divide_builtin_code): Likewise.
- (rs6000_mangle_decl_assembler_name): Add support for mangling the name
- of complex 128-bit multiply and divide built-in functions.
- * config/rs6000/rs6000.opt (building_libgcc): New target variable.
-
-gcc/testsuite/
-
- * gcc.target/powerpc/divic3-1.c: New test.
- * gcc.target/powerpc/divic3-2.c: Likewise.
- * gcc.target/powerpc/mulic3-1.c: Likewise.
- * gcc.target/powerpc/mulic3-2.c: Likewise.
-
-==================== work098, patch #3
-
-Add 'w' suffix for __ibm128 constants.
-
-In the documentation, we mention that 'w' or 'W' can be used as a suffix for
-__ibm128 constants. We never implemented this. This patch fixes that.
-
-2022-08-17 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/rs6000.cc (rs6000_c_mode_for_suffix): Allow 'w' or 'W'
- for __ibm128 constants.
-
-gcc/testsuite/
-
- * gcc.target/powerpc/ibm128-suffix.c: New test.
-
-==================== work098, patch #2
-
-Allow __ibm128 with -msoft-float (PR target/105334)
-
-This patch allows __ibm128 to be used on systems with software floating point
-enabled. Previously, we required hardware floating point to be enabled to use
-the __builtin_pack_ibm128 and __builtin_unpack_libm128 built-in functions. This
-fixes PR target/105334.
-
-
-2022-08-17 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- PR target/105334
- * config/rs6000/rs6000-builtins.cc (rs6000_init_builtins): Enable using
- the__ibm128 keyword on systems that either use the 128-bit IBM long
- double format for long double or support IEEE 128-bit.
- * config/rs6000/rs6000.cc (rs6000_init_libfuncs): Create IBM 128-bit
- floating point support functions on systems that support the __ibm128
- keyword.
- (rs6000_scalar_mode_supported_p): Likewise.
- * config/rs6000/rs6000.h (TARGET_IBM128): New macro.
- * config/rs6000/rs6000.md (@extenddf<mode>2_fprs): Allow IFmode to be
- converted even if long double is not 128-bits.
- (extenddf<mode>2_vsx): Likewise.
- (extendiftf2):Allow conversion on systems that support the __ibm128
- keyword.
- (extendtfif2): Likewise.
- (trunciftf2): Likewise.
- (trunctfif2): Likewise.
-
-==================== work098, patch #1
-
-Allow __ibm128 even if IEEE 128-bit floating point is not supported.
-
-This set of patches changes the GCC compiler to allow the use of the __ibm128
-keyword if we have IEEE 128-bit floating point support enabled or if long double
-is 128-bits.
-
-2022-08-17 Michael Meissner <meissner@linux.ibm.com>
-
-gcc/
-
- * config/rs6000/rs6000-builtins.cc (rs6000_init_builtins): Enable using
- the__ibm128 keyword on systems that either use the 128-bit IBM long
- double format for long double or support IEEE 128-bit.
- * config/rs6000/rs6000.cc (rs6000_init_libfuncs): Create IBM 128-bit
- floating point support functions on systems that support the __ibm128
- keyword.
- (rs6000_scalar_mode_supported_p): Likewise.
- * config/rs6000/rs6000.h (TARGET_IBM128): New macro.
- * config/rs6000/rs6000.md (@extenddf<mode>2_fprs): Allow IFmode to be
- converted even if long double is not 128-bits.
- (extenddf<mode>2_vsx): Likewise.
- (extendiftf2):Allow conversion on systems that support the __ibm128
- keyword.
- (extendtfif2): Likewise.
- (trunciftf2): Likewise.
- (trunctfif2): Likewise.
+==================== work098, patch #1 was reverted.
==================== work098, start branch
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index dfc6eb8aa83..b1fcc69bb60 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -119,31 +119,6 @@
return VSX_REGNO_P (REGNO (op));
})
-;; Return 1 if op is an IEEE 128-bit floating point type that is in a
-;; traditional Altivec register in order to do one of the IEEE 128-bit hardware
-;; instructions. We allow the operand to be converted from a mode that also
-;; supports IEEE 128-bit.
-(define_predicate "ieee128_operand"
- (match_code "reg,subreg,float_extend,float_truncate")
-{
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (!FLOAT128_IEEE_P (mode))
- return 0;
-
- /* Allow conversions from another IEEE 128-bit mode. */
- if (GET_CODE (op) == FLOAT_EXTEND || GET_CODE (op) == FLOAT_TRUNCATE)
- {
- op = XEXP (op, 0);
- mode = GET_MODE (op);
- if (!FLOAT128_IEEE_P (mode))
- return 0;
- }
-
- return altivec_register_operand (op, mode);
-})
-
;; Return 1 if op is a vector register that operates on floating point vectors
;; (either altivec or VSX).
(define_predicate "vfloat_operand"
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 30c7e76c486..12afa86854c 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -713,7 +713,7 @@ rs6000_init_builtins (void)
For IEEE 128-bit floating point, always create the type __ieee128. If the
user used -mfloat128, rs6000-c.cc will create a define from __float128 to
__ieee128. */
- if (TARGET_IBM128)
+ if (TARGET_LONG_DOUBLE_128 && (!TARGET_IEEEQUAD || TARGET_FLOAT128_TYPE))
{
if (!TARGET_IEEEQUAD)
ibm128_float_type_node = long_double_type_node;
@@ -733,10 +733,10 @@ rs6000_init_builtins (void)
if (TARGET_FLOAT128_TYPE)
{
- /* Always make the type used by __float128 to be the same as the
- _Float128 type. The C23 standard will want long double to be a
- different type than _Float128, so don't use the long double type. */
- ieee128_float_type_node = float128_type_node;
+ if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
+ ieee128_float_type_node = long_double_type_node;
+ else
+ ieee128_float_type_node = float128_type_node;
t = build_qualified_type (ieee128_float_type_node, TYPE_QUAL_CONST);
lang_hooks.types.register_builtin_type (ieee128_float_type_node,
"__ieee128");
@@ -3243,13 +3243,13 @@ htm_expand_builtin (bifdata *bifaddr, rs6000_gen_builtins fcode,
/* Expand an expression EXP that calls a built-in function,
with result going to TARGET if that's convenient
- (and in mode RESULT_MODE if that's convenient).
+ (and in mode MODE if that's convenient).
SUBTARGET may be used as the target for computing one of EXP's operands.
IGNORE is nonzero if the value is to be ignored.
Use the new builtin infrastructure. */
rtx
rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
- machine_mode result_mode, int ignore)
+ machine_mode /* mode */, int ignore)
{
tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
enum rs6000_gen_builtins fcode
@@ -3257,10 +3257,22 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
size_t uns_fcode = (size_t)fcode;
enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
- /* If we have a KFmode built-in function and we want TFmode because long
- double uses the IEEE 128-bit format, we have to convert the KFmode
- built-in to the similar TFmode built-in. */
- if (result_mode == TFmode && FLOAT128_IEEE_P (TFmode))
+ /* TODO: The following commentary and code is inherited from the original
+ builtin processing code. The commentary is a bit confusing, with the
+ intent being that KFmode is always IEEE-128, IFmode is always IBM
+ double-double, and TFmode is the current long double. The code is
+ confusing in that it converts from KFmode to TFmode pattern names,
+ when the other direction is more intuitive. Try to address this. */
+
+ /* We have two different modes (KFmode, TFmode) that are the IEEE
+ 128-bit floating point type, depending on whether long double is the
+ IBM extended double (KFmode) or long double is IEEE 128-bit (TFmode).
+ It is simpler if we only define one variant of the built-in function,
+ and switch the code when defining it, rather than defining two built-
+ ins and using the overload table in rs6000-c.cc to switch between the
+ two. If we don't have the proper assembler, don't do this switch
+ because CODE_FOR_*kf* and CODE_FOR_*tf* will be CODE_FOR_nothing. */
+ if (FLOAT128_IEEE_P (TFmode))
switch (icode)
{
case CODE_FOR_sqrtkf2_odd:
@@ -3318,15 +3330,6 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
break;
}
- /* If we have a IFmode built-in function, we might need to map that built-in
- function to use TFmode instead of IFmode. */
- if (result_mode == TFmode && icode == CODE_FOR_packif)
- icode = CODE_FOR_packtf;
-
- else if (icode == CODE_FOR_unpackif
- && TYPE_MODE (TREE_TYPE (CALL_EXPR_ARG (exp, 0))) == TFmode)
- icode = CODE_FOR_unpacktf;
-
/* In case of "#pragma target" changes, we initialize all builtins
but check for actual availability now, during expand time. For
invalid builtins, generate a normal call. */
@@ -3446,6 +3449,22 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
gcc_unreachable ();
}
+ if (bif_is_ibm128 (*bifaddr) && TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
+ {
+ if (fcode == RS6000_BIF_PACK_IF)
+ {
+ icode = CODE_FOR_packtf;
+ fcode = RS6000_BIF_PACK_TF;
+ uns_fcode = (size_t) fcode;
+ }
+ else if (fcode == RS6000_BIF_UNPACK_IF)
+ {
+ icode = CODE_FOR_unpacktf;
+ fcode = RS6000_BIF_UNPACK_TF;
+ uns_fcode = (size_t) fcode;
+ }
+ }
+
/* TRUE iff the built-in function returns void. */
bool void_func = TREE_TYPE (TREE_TYPE (fndecl)) == void_type_node;
/* Position of first argument (0 for void-returning functions, else 1). */
@@ -3598,21 +3617,7 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
for (int i = 0; i < nargs; i++)
if (!insn_data[icode].operand[i+k].predicate (op[i], mode[i+k]))
- {
- /* copy_to_mode_reg will abort if the mode we want to copy to is
- different from the operand. If the modes are different, do a
- convert instead of copy. This can show up if we are wanting KFmode
- and we get a TFmode when long double uses the IEEE 128-bit
- encoding. */
- if (GET_MODE (op[i]) != mode[i+k])
- {
- rtx tmp = gen_reg_rtx (mode[i+k]);
- convert_move (tmp, op[i], 0);
- op[i] = tmp;
- }
- else
- op[i] = copy_to_mode_reg (mode[i+k], op[i]);
- }
+ op[i] = copy_to_mode_reg (mode[i+k], op[i]);
rtx pat;
diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
index 11de8389fd6..4d051b90658 100644
--- a/gcc/config/rs6000/rs6000-c.cc
+++ b/gcc/config/rs6000/rs6000-c.cc
@@ -780,14 +780,6 @@ rs6000_cpu_cpp_builtins (cpp_reader *pfile)
|| DEFAULT_ABI == ABI_ELFv2
|| (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
builtin_define ("__STRUCT_PARM_ALIGN__=16");
-
- /* Store whether or not we are building libgcc. This is needed to disable
- generating the alternate names for 128-bit complex multiply and divide.
- We need to disable generating __multc3, __divtc3, __mulkc3, and __divkc3
- when we are building those functions in libgcc. The variable
- flag_building_libgcc is only available for the C family of front-ends.
- We set this variable here to disable generating the alternate names. */
- building_libgcc = flag_building_libgcc;
}
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 261d8853d4d..df491bee2ea 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -10913,23 +10913,26 @@ init_float128_ibm (machine_mode mode)
set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
- set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
- set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
- set_optab_libfunc (ne_optab, mode, "__gcc_qne");
- set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
- set_optab_libfunc (ge_optab, mode, "__gcc_qge");
- set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
- set_optab_libfunc (le_optab, mode, "__gcc_qle");
- set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
-
- set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
- set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
- set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
- set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
- set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
- set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
- set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
- set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
+ if (!TARGET_HARD_FLOAT)
+ {
+ set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
+ set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
+ set_optab_libfunc (ne_optab, mode, "__gcc_qne");
+ set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
+ set_optab_libfunc (ge_optab, mode, "__gcc_qge");
+ set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
+ set_optab_libfunc (le_optab, mode, "__gcc_qle");
+ set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
+
+ set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
+ set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
+ set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
+ set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
+ set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
+ set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
+ set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
+ set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
+ }
}
else
{
@@ -10966,6 +10969,26 @@ init_float128_ibm (machine_mode mode)
}
}
+/* Create a decl for either complex long double multiply or complex long double
+ divide when long double is IEEE 128-bit floating point. We can't use
+ __multc3 and __divtc3 because the original long double using IBM extended
+ double used those names. The complex multiply/divide functions are encoded
+ as builtin functions with a complex result and 4 scalar inputs. */
+
+static void
+create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
+{
+ tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
+ name, NULL_TREE);
+
+ set_builtin_decl (fncode, fndecl, true);
+
+ if (TARGET_DEBUG_BUILTIN)
+ fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
+
+ return;
+}
+
/* Set up IEEE 128-bit floating point routines. Use different names if the
arguments can be passed in a vector register. The historical PowerPC
implementation of IEEE 128-bit floating point used _q_<op> for the names, so
@@ -10977,6 +11000,32 @@ init_float128_ieee (machine_mode mode)
{
if (FLOAT128_VECTOR_P (mode))
{
+ static bool complex_muldiv_init_p = false;
+
+ /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
+ we have clone or target attributes, this will be called a second
+ time. We want to create the built-in function only once. */
+ if (mode == TFmode && TARGET_IEEEQUAD && !complex_muldiv_init_p)
+ {
+ complex_muldiv_init_p = true;
+ built_in_function fncode_mul =
+ (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
+ - MIN_MODE_COMPLEX_FLOAT);
+ built_in_function fncode_div =
+ (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
+ - MIN_MODE_COMPLEX_FLOAT);
+
+ tree fntype = build_function_type_list (complex_long_double_type_node,
+ long_double_type_node,
+ long_double_type_node,
+ long_double_type_node,
+ long_double_type_node,
+ NULL_TREE);
+
+ create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
+ create_complex_muldiv ("__divkc3", fncode_div, fntype);
+ }
+
set_optab_libfunc (add_optab, mode, "__addkf3");
set_optab_libfunc (sub_optab, mode, "__subkf3");
set_optab_libfunc (neg_optab, mode, "__negkf2");
@@ -11066,11 +11115,10 @@ rs6000_init_libfuncs (void)
{
/* __float128 support. */
if (TARGET_FLOAT128_TYPE)
- init_float128_ieee (KFmode);
-
- /* __ibm128 support. */
- if (TARGET_IBM128)
- init_float128_ibm (IFmode);
+ {
+ init_float128_ibm (IFmode);
+ init_float128_ieee (KFmode);
+ }
/* AIX/Darwin/64-bit Linux quad floating point routines. */
if (TARGET_LONG_DOUBLE_128)
@@ -23704,9 +23752,7 @@ rs6000_scalar_mode_supported_p (scalar_mode mode)
if (DECIMAL_FLOAT_MODE_P (mode))
return default_decimal_float_supported_p ();
- else if (TARGET_FLOAT128_TYPE && mode == KFmode)
- return true;
- else if (TARGET_IBM128 && mode == IFmode)
+ else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
return true;
else
return default_scalar_mode_supported_p (mode);
@@ -23724,8 +23770,13 @@ rs6000_libgcc_floating_mode_supported_p (scalar_float_mode mode)
case E_TFmode:
return true;
+ /* We only return true for KFmode if IEEE 128-bit types are supported, and
+ if long double does not use the IEEE 128-bit format. If long double
+ uses the IEEE 128-bit format, it will use TFmode and not KFmode.
+ Because the code will not use KFmode in that case, there will be aborts
+ because it can't find KFmode in the Floatn types. */
case E_KFmode:
- return TARGET_FLOAT128_TYPE;
+ return TARGET_FLOAT128_TYPE && !TARGET_IEEEQUAD;
default:
return false;
@@ -23759,7 +23810,7 @@ rs6000_floatn_mode (int n, bool extended)
case 64:
if (TARGET_FLOAT128_TYPE)
- return KFmode;
+ return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
else
return opt_scalar_float_mode ();
@@ -23783,7 +23834,7 @@ rs6000_floatn_mode (int n, bool extended)
case 128:
if (TARGET_FLOAT128_TYPE)
- return KFmode;
+ return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
else
return opt_scalar_float_mode ();
@@ -23798,11 +23849,18 @@ rs6000_floatn_mode (int n, bool extended)
static machine_mode
rs6000_c_mode_for_suffix (char suffix)
{
- if (TARGET_FLOAT128_TYPE && (suffix == 'q' || suffix == 'Q'))
- return TYPE_MODE (float128_type_node);
+ if (TARGET_FLOAT128_TYPE)
+ {
+ if (suffix == 'q' || suffix == 'Q')
+ return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
- if (TARGET_IBM128 && (suffix == 'w' || suffix == 'W'))
- return TYPE_MODE (ibm128_float_type_node);
+ /* At the moment, we are not defining a suffix for IBM extended double.
+ If/when the default for -mabi=ieeelongdouble is changed, and we want
+ to support __ibm128 constants in legacy library code, we may need to
+ re-evalaute this decision. Currently, c-lex.cc only supports 'w' and
+ 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
+ __float80 constants. */
+ }
return VOIDmode;
}
@@ -27912,25 +27970,6 @@ rs6000_starting_frame_offset (void)
return RS6000_STARTING_FRAME_OFFSET;
}
-/* Internal function to return the built-in function id for the complex
- multiply operation for a given mode. */
-
-static inline built_in_function
-complex_multiply_builtin_code (machine_mode mode)
-{
- return (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + mode
- - MIN_MODE_COMPLEX_FLOAT);
-}
-
-/* Internal function to return the built-in function id for the complex divide
- operation for a given mode. */
-
-static inline built_in_function
-complex_divide_builtin_code (machine_mode mode)
-{
- return (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + mode
- - MIN_MODE_COMPLEX_FLOAT);
-}
/* On 64-bit Linux and Freebsd systems, possibly switch the long double library
function names from <foo>l to <foo>f128 if the default long double type is
@@ -27949,54 +27988,11 @@ complex_divide_builtin_code (machine_mode mode)
only do this transformation if the __float128 type is enabled. This
prevents us from doing the transformation on older 32-bit ports that might
have enabled using IEEE 128-bit floating point as the default long double
- type.
-
- We also use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change the
- function names used for complex multiply and divide to the appropriate
- names. */
+ type. */
static tree
rs6000_mangle_decl_assembler_name (tree decl, tree id)
{
- /* Handle complex multiply/divide. For IEEE 128-bit, use __mulkc3 or
- __divkc3 and for IBM 128-bit use __multc3 and __divtc3. */
- if ((TARGET_FLOAT128_TYPE || TARGET_IBM128)
- && !building_libgcc
- && TREE_CODE (decl) == FUNCTION_DECL
- && DECL_IS_UNDECLARED_BUILTIN (decl)
- && DECL_BUILT_IN_CLASS (decl) == BUILT_IN_NORMAL)
- {
- built_in_function id = DECL_FUNCTION_CODE (decl);
- const char *newname = NULL;
-
- if (id == complex_multiply_builtin_code (KCmode))
- newname = "__mulkc3";
-
- else if (id == complex_multiply_builtin_code (ICmode))
- newname = "__multc3";
-
- else if (id == complex_multiply_builtin_code (TCmode))
- newname = (TARGET_IEEEQUAD) ? "__mulkc3" : "__multc3";
-
- else if (id == complex_divide_builtin_code (KCmode))
- newname = "__divkc3";
-
- else if (id == complex_divide_builtin_code (ICmode))
- newname = "__divtc3";
-
- else if (id == complex_divide_builtin_code (TCmode))
- newname = (TARGET_IEEEQUAD) ? "__divkc3" : "__divtc3";
-
- if (newname)
- {
- if (TARGET_DEBUG_BUILTIN)
- fprintf (stderr, "Map complex mul/div => %s\n", newname);
-
- return get_identifier (newname);
- }
- }
-
- /* Map long double built-in functions if long double is IEEE 128-bit. */
if (TARGET_FLOAT128_TYPE && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
&& TREE_CODE (decl) == FUNCTION_DECL
&& DECL_IS_UNDECLARED_BUILTIN (decl)
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index f58f5f3f355..ad9bf0f7358 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -337,7 +337,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
#define FLOAT128_IBM_P(MODE) \
((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
&& ((MODE) == TFmode || (MODE) == TCmode)) \
- || ((MODE) == IFmode || (MODE) == ICmode))
+ || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
/* Helper macros to say whether a 128-bit floating point type can go in a
single vector register, or whether it needs paired scalar values. */
@@ -564,12 +564,6 @@ extern int rs6000_vector_align[];
&& TARGET_P8_VECTOR \
&& TARGET_POWERPC64)
-/* Whether the __ibm128 keyword is allowed. Any system that supports _Float128
- is assumed to be capable of supporting __ibm128. Similarly if the long
- double size is 128 bits, we assume __ibm128 is supported. We don't want to
- support it on a system without existing 128-bit long doubles. */
-#define TARGET_IBM128 (TARGET_FLOAT128_TYPE || TARGET_LONG_DOUBLE_128)
-
/* Inlining allows targets to define the meanings of bits in target_info
field of ipa_fn_summary by itself, the used bits for rs6000 are listed
below. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e0f6a3749a6..1367a2cb779 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -543,6 +543,12 @@
; Iterator for 128-bit VSX types for pack/unpack
(define_mode_iterator FMOVE128_VSX [V1TI KF])
+; Iterators for converting to/from TFmode
+(define_mode_iterator IFKF [IF KF])
+
+; Constraints for moving IF/KFmode.
+(define_mode_attr IFKF_reg [(IF "d") (KF "wa")])
+
; Whether a floating point move is ok, don't allow SD without hardware FP
(define_mode_attr fmove_ok [(SF "")
(DF "")
@@ -8580,7 +8586,8 @@
(float_extend:IBM128
(match_operand:DF 1 "nonimmediate_operand" "d,m,d")))
(use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))]
- "!TARGET_VSX && TARGET_HARD_FLOAT && FLOAT128_IBM_P (<MODE>mode)"
+ "!TARGET_VSX && TARGET_HARD_FLOAT
+ && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
[(set (match_dup 3) (match_dup 1))
@@ -8597,7 +8604,7 @@
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d")
(float_extend:IBM128
(match_operand:DF 1 "nonimmediate_operand" "wa,m")))]
- "TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)"
+ "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
[(set (match_dup 2) (match_dup 1))
@@ -9054,7 +9061,7 @@
(define_expand "extendiftf2"
[(set (match_operand:TF 0 "gpc_reg_operand")
(float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_IBM128"
+ "TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
DONE;
@@ -9069,15 +9076,6 @@
DONE;
})
-(define_expand "extendkfif2"
- [(set (match_operand:IF 0 "gpc_reg_operand")
- (float_extend:IF (match_operand:KF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
(define_expand "extendtfkf2"
[(set (match_operand:KF 0 "gpc_reg_operand")
(float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))]
@@ -9090,7 +9088,7 @@
(define_expand "extendtfif2"
[(set (match_operand:IF 0 "gpc_reg_operand")
(float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_IBM128"
+ "TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
DONE;
@@ -9099,7 +9097,7 @@
(define_expand "trunciftf2"
[(set (match_operand:TF 0 "gpc_reg_operand")
(float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))]
- "TARGET_IBM128"
+ "TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
DONE;
@@ -9114,15 +9112,6 @@
DONE;
})
-(define_expand "trunckfif2"
- [(set (match_operand:IF 0 "gpc_reg_operand")
- (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))]
- "TARGET_FLOAT128_TYPE"
-{
- rs6000_expand_float128_convert (operands[0], operands[1], false);
- DONE;
-})
-
(define_expand "trunckftf2"
[(set (match_operand:TF 0 "gpc_reg_operand")
(float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))]
@@ -9135,79 +9124,37 @@
(define_expand "trunctfif2"
[(set (match_operand:IF 0 "gpc_reg_operand")
(float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))]
- "TARGET_IBM128"
+ "TARGET_FLOAT128_TYPE"
{
rs6000_expand_float128_convert (operands[0], operands[1], false);
DONE;
})
-;; Convert between KFmode and TFmode when -mabi=ieeelongdouble
-(define_insn_and_split "*extendkftf2_internal"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa")
+(define_insn_and_split "*extend<mode>tf2_internal"
+ [(set (match_operand:TF 0 "gpc_reg_operand" "=<IFKF_reg>")
(float_extend:TF
- (match_operand:KF 1 "gpc_reg_operand" "0,wa")))]
- "FLOAT128_IEEE_P (TFmode)"
+ (match_operand:IFKF 1 "gpc_reg_operand" "<IFKF_reg>")))]
+ "TARGET_FLOAT128_TYPE
+ && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 2))]
{
operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1]));
-}
- [(set_attr "type" "vecsimple")])
+})
-(define_insn_and_split "*extendtfkf2_internal"
- [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa")
- (float_extend:KF
- (match_operand:TF 1 "gpc_reg_operand" "0,wa")))]
- "FLOAT128_IEEE_P (TFmode)"
+(define_insn_and_split "*extendtf<mode>2_internal"
+ [(set (match_operand:IFKF 0 "gpc_reg_operand" "=<IFKF_reg>")
+ (float_extend:IFKF
+ (match_operand:TF 1 "gpc_reg_operand" "<IFKF_reg>")))]
+ "TARGET_FLOAT128_TYPE
+ && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (<MODE>mode)"
"#"
"&& reload_completed"
[(set (match_dup 0) (match_dup 2))]
{
- operands[2] = gen_rtx_REG (KFmode, REGNO (operands[1]));
-}
- [(set_attr "type" "vecsimple")])
-
-;; Convert between IFmode and TFmode when -mabi=ibmlongdouble
-(define_insn_and_split "*extendiftf2_internal"
- [(set (match_operand:TF 0 "gpc_reg_operand" "=d,&d")
- (float_extend:TF
- (match_operand:IF 1 "input_operand" "0,d")))]
- "FLOAT128_IBM_P (TFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 4) (match_dup 5))]
-{
- unsigned int op0_regno = reg_or_subregno (operands[0]);
- unsigned int op1_regno = reg_or_subregno (operands[1]);
- operands[2] = gen_rtx_REG (DFmode, op0_regno);
- operands[3] = gen_rtx_REG (DFmode, op1_regno);
- operands[4] = gen_rtx_REG (DFmode, op0_regno + 1);
- operands[5] = gen_rtx_REG (DFmode, op1_regno + 1);
-}
- [(set_attr "type" "two")
- (set_attr "num_insns" "2")])
-
-(define_insn_and_split "*extendtfif2_internal"
- [(set (match_operand:IF 0 "gpc_reg_operand" "=d,&d")
- (float_extend:IF
- (match_operand:TF 1 "input_operand" "0,d")))]
- "FLOAT128_IBM_P (TFmode)"
- "#"
- "&& reload_completed"
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 4) (match_dup 5))]
-{
- unsigned int op0_regno = reg_or_subregno (operands[0]);
- unsigned int op1_regno = reg_or_subregno (operands[1]);
- operands[2] = gen_rtx_REG (DFmode, op0_regno);
- operands[3] = gen_rtx_REG (DFmode, op1_regno);
- operands[4] = gen_rtx_REG (DFmode, op0_regno + 1);
- operands[5] = gen_rtx_REG (DFmode, op1_regno + 1);
-}
- [(set_attr "type" "two")
- (set_attr "num_insns" "2")])
+ operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
+})
;; Reload helper functions used by rs6000_secondary_reload. The patterns all
@@ -14984,7 +14931,7 @@
(define_insn_and_split "trunc<mode>sf2_hw"
[(set (match_operand:SF 0 "vsx_register_operand" "=wa")
(float_truncate:SF
- (match_operand:IEEE128 1 "ieee128_operand" "v")))
+ (match_operand:IEEE128 1 "altivec_register_operand" "v")))
(clobber (match_scratch:DF 2 "=v"))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"#"
@@ -15215,8 +15162,8 @@
(define_insn "add<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_ADD_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsaddqpo %0,%1,%2"
@@ -15226,8 +15173,8 @@
(define_insn "sub<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_SUB_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssubqpo %0,%1,%2"
@@ -15237,8 +15184,8 @@
(define_insn "mul<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_MUL_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmulqpo %0,%1,%2"
@@ -15248,8 +15195,8 @@
(define_insn "div<mode>3_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_DIV_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsdivqpo %0,%1,%2"
@@ -15259,7 +15206,7 @@
(define_insn "sqrt<mode>2_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_SQRT_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xssqrtqpo %0,%1"
@@ -15269,9 +15216,9 @@
(define_insn "fma<mode>4_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")
- (match_operand:IEEE128 3 "ieee128_operand" "0")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")
+ (match_operand:IEEE128 3 "altivec_register_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmaddqpo %0,%1,%2"
@@ -15281,10 +15228,10 @@
(define_insn "*fms<mode>4_odd"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "%v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")
(neg:IEEE128
- (match_operand:IEEE128 3 "ieee128_operand" "0"))]
+ (match_operand:IEEE128 3 "altivec_register_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsmsubqpo %0,%1,%2"
@@ -15295,9 +15242,9 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "%v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")
- (match_operand:IEEE128 3 "ieee128_operand" "0")]
+ [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")
+ (match_operand:IEEE128 3 "altivec_register_operand" "0")]
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmaddqpo %0,%1,%2"
@@ -15308,10 +15255,10 @@
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(neg:IEEE128
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "%v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "%v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")
(neg:IEEE128
- (match_operand:IEEE128 3 "ieee128_operand" "0"))]
+ (match_operand:IEEE128 3 "altivec_register_operand" "0"))]
UNSPEC_FMA_ROUND_TO_ODD)))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xsnmsubqpo %0,%1,%2"
@@ -15320,7 +15267,7 @@
(define_insn "trunc<mode>df2_odd"
[(set (match_operand:DF 0 "vsx_register_operand" "=v")
- (unspec:DF [(match_operand:IEEE128 1 "ieee128_operand" "v")]
+ (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_TRUNC_ROUND_TO_ODD))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscvqpdpo %0,%1"
@@ -15330,8 +15277,8 @@
;; IEEE 128-bit comparisons
(define_insn "*cmp<mode>_hw"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
- (compare:CCFP (match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")))]
+ (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")))]
"TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
"xscmpuqp %0,%1,%2"
[(set_attr "type" "veccmp")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 1299d47e5b2..b227bf96888 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -100,10 +100,6 @@ unsigned int rs6000_recip_control
TargetVariable
unsigned int rs6000_debug
-;; Whether we are building libgcc or not.
-TargetVariable
-bool building_libgcc = false
-
;; Whether to enable the -mfloat128 stuff without necessarily enabling the
;; __float128 keyword.
TargetSave
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 03146223d1d..e226a93bbe5 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5087,7 +5087,7 @@
;; VSX Scalar Extract Exponent Quad-Precision
(define_insn "xsxexpqp_<mode>"
[(set (match_operand:DI 0 "altivec_register_operand" "=v")
- (unspec:DI [(match_operand:IEEE128 1 "ieee128_operand" "v")]
+ (unspec:DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_VSX_SXEXPDP))]
"TARGET_P9_VECTOR"
"xsxexpqp %0,%1"
@@ -5105,7 +5105,7 @@
;; VSX Scalar Extract Significand Quad-Precision
(define_insn "xsxsigqp_<mode>"
[(set (match_operand:TI 0 "altivec_register_operand" "=v")
- (unspec:TI [(match_operand:IEEE128 1 "ieee128_operand" "v")]
+ (unspec:TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")]
UNSPEC_VSX_SXSIG))]
"TARGET_P9_VECTOR"
"xsxsigqp %0,%1"
@@ -5124,7 +5124,7 @@
(define_insn "xsiexpqpf_<mode>"
[(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:DI 2 "altivec_register_operand" "v")]
UNSPEC_VSX_SIEXPQP))]
"TARGET_P9_VECTOR"
@@ -5200,8 +5200,8 @@
[(set (match_dup 3)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ [(match_operand:IEEE128 1 "vsx_register_operand" "v")
+ (match_operand:IEEE128 2 "vsx_register_operand" "v")]
UNSPEC_VSX_SCMPEXPQP)
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=r")
@@ -5221,8 +5221,8 @@
(define_insn "*xscmpexpqp"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
(compare:CCFP
- (unspec:IEEE128 [(match_operand:IEEE128 1 "ieee128_operand" "v")
- (match_operand:IEEE128 2 "ieee128_operand" "v")]
+ (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+ (match_operand:IEEE128 2 "altivec_register_operand" "v")]
UNSPEC_VSX_SCMPEXPQP)
(match_operand:SI 3 "zero_constant" "j")))]
"TARGET_P9_VECTOR"
@@ -5238,7 +5238,7 @@
[(set (match_dup 3)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))
@@ -5276,7 +5276,7 @@
[(set (match_dup 2)
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
(const_int 0)]
UNSPEC_VSX_STSTDC)
(const_int 0)))
@@ -5310,7 +5310,7 @@
[(set (match_operand:CCFP 0 "" "=y")
(compare:CCFP
(unspec:IEEE128
- [(match_operand:IEEE128 1 "ieee128_operand" "v")
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
(match_operand:SI 2 "u7bit_cint_operand" "n")]
UNSPEC_VSX_STSTDC)
(const_int 0)))]
diff --git a/gcc/testsuite/gcc.target/powerpc/divic3-1.c b/gcc/testsuite/gcc.target/powerpc/divic3-1.c
deleted file mode 100644
index 1cc6b1be904..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/divic3-1.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-require-effective-target longdouble128 } */
-/* { dg-require-effective-target ppc_float128_sw } */
-/* { dg-options "-O2 -mpower8-vector -mabi=ieeelongdouble -Wno-psabi" } */
-
-/* Check that complex divide generates the right call for __ibm128 when long
- double is IEEE 128-bit floating point. */
-
-typedef _Complex long double c_ibm128_t __attribute__((mode(__IC__)));
-
-void
-divide (c_ibm128_t *p, c_ibm128_t *q, c_ibm128_t *r)
-{
- *p = *q / *r;
-}
-
-/* { dg-final { scan-assembler "bl __divtc3" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/divic3-2.c b/gcc/testsuite/gcc.target/powerpc/divic3-2.c
deleted file mode 100644
index 8ff342e0116..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/divic3-2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-require-effective-target longdouble128 } */
-/* { dg-options "-O2 -mpower8-vector -mabi=ibmlongdouble -Wno-psabi" } */
-
-/* Check that complex divide generates the right call for __ibm128 when long
- double is IBM 128-bit floating point. */
-
-typedef _Complex long double c_ibm128_t __attribute__((mode(__TC__)));
-
-void
-divide (c_ibm128_t *p, c_ibm128_t *q, c_ibm128_t *r)
-{
- *p = *q / *r;
-}
-
-/* { dg-final { scan-assembler "bl __divtc3" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/ibm128-suffix.c b/gcc/testsuite/gcc.target/powerpc/ibm128-suffix.c
deleted file mode 100644
index ff619860409..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/ibm128-suffix.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target longdouble128 } */
-/* { dg-options "-O2" } */
-
-/* See if the 'w' suffix is accepted for __ibm128. */
-#ifndef NUMBER
-#define NUMBER 123456789012345678901234567890123456789E-10
-#endif
-
-#define GLUE2(X,Y) X ## Y
-#define GLUE(X,Y) GLUE2(X,Y)
-
-__ibm128 x = GLUE (NUMBER, w);
diff --git a/gcc/testsuite/gcc.target/powerpc/mulic3-1.c b/gcc/testsuite/gcc.target/powerpc/mulic3-1.c
deleted file mode 100644
index 4cd773c4b06..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/mulic3-1.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-require-effective-target longdouble128 } */
-/* { dg-require-effective-target ppc_float128_sw } */
-/* { dg-options "-O2 -mpower8-vector -mabi=ieeelongdouble -Wno-psabi" } */
-
-/* Check that complex multiply generates the right call for __ibm128 when long
- double is IEEE 128-bit floating point. */
-
-typedef _Complex long double c_ibm128_t __attribute__((mode(__IC__)));
-
-void
-multiply (c_ibm128_t *p, c_ibm128_t *q, c_ibm128_t *r)
-{
- *p = *q * *r;
-}
-
-/* { dg-final { scan-assembler "bl __multc3" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/mulic3-2.c b/gcc/testsuite/gcc.target/powerpc/mulic3-2.c
deleted file mode 100644
index 36fe8bc3061..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/mulic3-2.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target powerpc_p8vector_ok } */
-/* { dg-require-effective-target longdouble128 } */
-/* { dg-options "-O2 -mpower8-vector -mabi=ibmlongdouble -Wno-psabi" } */
-
-/* Check that complex multiply generates the right call for __ibm128 when long
- double is IBM 128-bit floating point. */
-
-typedef _Complex long double c_ibm128_t __attribute__((mode(__TC__)));
-
-void
-multiply (c_ibm128_t *p, c_ibm128_t *q, c_ibm128_t *r)
-{
- *p = *q * *r;
-}
-
-/* { dg-final { scan-assembler "bl __multc3" } } */
More information about the Gcc-cvs
mailing list