[gcc(refs/users/meissner/heads/work087)] Update ChangeLog.meissner.

[Michael Meissner]

https://gcc.gnu.org/g:7408714081fdd76e3280701d8c575791f089f5cd

commit 7408714081fdd76e3280701d8c575791f089f5cd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 27 11:41:02 2022 -0400

    Update ChangeLog.meissner.
    
    2022-04-26   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
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 gcc/ChangeLog.meissner | 104 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 104 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index b93cf1374ce..6c290ca3f84 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,107 @@
+==================== work087, patch #2:
+
+Add options to control load/store vector pair generation.
+
+This patch adds options to allow disabling generating either the load
+vector pair instructions (lxvp, lxvpx, plxvp) or the store vector pair
+instructions (stxvp, stxvpx, pstxvp).
+
+2022-04-27   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	* config/rs6000/mma.md (movoo): Add support to suppress load/store
+	vector pair instructions.
+	(movxo): Likewise.
+	* config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): Disable
+	indexed loads for vector pair if either lxvp/stxvp are disabled.
+	(rs6000_split_multireg_move): Do not split vector quad to vector
+	pair if lxvp/stxvp is disabled.
+	* config/rs6000/rs6000.md (isa attribute): Add lxvp and stxvp
+	attributes.
+	(enabled attribute): Add lxvp/stxvp support.
+	* config/rs6000/rs6000.opt (-mload-vector-pair): New option.
+	(-mstore-vector-pair): New option.
+
+gcc/testsuite/
+	* gcc.target/powerpc/p10-load-vector-pair-1.c: New test.
+	* gcc.target/powerpc/p10-load-vector-pair-2.c: New test.
+	* gcc.target/powerpc/p10-store-vector-pair-1.c: New test.
+	* gcc.target/powerpc/p10-store-vector-pair-2.c: New test.
+
+==================== work087, patch #1:
+
+Eliminate power8 fusion options, use power8 tuning, PR target/102059
+
+This is V4 of the patch.  Compared to V3 of the patch, GCC will just
+ignore -m{,no-}power8-fusion and -m{,no-}power8-fusion-sign.
+
+The splitting of signed halfword and word loads into unsigned load and
+sign extension is now suppressed with -Os, but it is done normally if we
+are not optimizing for space.
+
+The power8 fusion support used to be set automatically when -mcpu=power8 or
+-mtune=power8 was used, and it was cleared for other cpu's.  However, if you
+used the target attribute or target #pragma to change the default cpu type or
+tuning, you would get an error that a target specifiction option mismatch
+occurred.
+
+This occurred because the rs6000_can_inline_p function just compares the ISA
+bits between the called inline function and the caller.  If the ISA flags of
+the called function is not a subset of the ISA flags of the caller, we won't do
+the inlinging.  When a power9 or power10 function inlines a function that is
+explicitly compiled for power8, the power8 function has the power8 fusion bits
+set and the power9 or power10 functions do not have the fusion bits set.
+
+This code makes the -mpower8-fusion option a nop.  It is accepted without
+warning, but it does nothing.  Power8 fusion is only enabled if we are tuning
+for a power8.
+
+The undocumented -mpower8-fusion-sign option is also made into a nop.
+
+I left in the pragma target and attribute target support for power8-fusion, but
+using it doesn't do anything now.  This is because I told the customer who
+encountered this problem that one solution was to add an explicit
+no-power8-fusion option in their target pragma or attribute to work around the
+problem.
+
+I have tested this patch on a little endian power10 system.  I have tested
+previous versions on little endian power9 and big endian power8 systems.
+Can I apply this patch to the master branch?
+
+If it is accepted, I will produce a similar patch for back porting to GCC 11
+and GCC 10.
+
+2022-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/102059
+	* config/rs6000/rs6000-cpus.def (OTHER_FUSION_MASKS): Delete.
+	(ISA_3_0_MASKS_SERVER): Don't clear the fusion masks.
+	(POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION.
+	* config/rs6000/rs6000.cc (rs6000_option_override_internal):
+	Delete code that set the power8 fusion options automatically.
+	(rs6000_opt_masks): Allow #pragma target and attribute target
+	power8-fusion option for backwards compatibility.
+	(rs6000_print_options_internal): Skip printing backward
+	compatibility options that are just ignored.
+	* config/rs6000/rs6000.h (TARGET_P8_FUSION): New macro.
+	(TARGET_P8_FUSION_SIGN): Likewise.
+	(MASK_P8_FUSION): Delete.
+	* config/rs6000/rs6000.opt (-mpower8-fusion): Recognize the option but
+	ignore it completely.
+	(-mpower8-fusion-sign): Likewise.
+	* doc/invoke.texi (RS/6000 and PowerPC Options): Delete
+	-mpower8-fusion.
+
+gcc/testsuite/
+	PR target/102059
+	* gcc.dg/lto/pr102059-1_0.c: Remove -mno-power8-fusion.
+	* gcc.dg/lto/pr102059-2_0.c: Likewise.
+	* gcc.target/powerpc/pr102059-3.c: Likewise.
+	* gcc.target/powerpc/pr102059-4.c: New test.
+
+==================== work087, head:
+
 2022-04-26   Michael Meissner  <meissner@linux.ibm.com>
 
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