[gcc(refs/users/wschmidt/heads/builtins8)] rs6000: **separate and squash me**
William Schmidt
wschmidt@gcc.gnu.org
Wed Mar 24 15:41:06 GMT 2021
https://gcc.gnu.org/g:da67a7b4c9a71e0421062199925c43e61d35f710
commit da67a7b4c9a71e0421062199925c43e61d35f710
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Mon Mar 22 17:13:43 2021 -0500
rs6000: **separate and squash me**
2021-03-22 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtin-new.def (MFTB): Flag as 32bit.
(LD_ELEMREV_*): Flag as endian.
(ST_ELEMREV_*): Likewise.
(GET_TEXASR): Return long.
(GET_TEXASRU): Likewise.
(GET_TFHAR): Likewise.
(GET_TFIAR): Likewise.
(SET_TEXASR): Pass long.
(SET_TEXASR): Likewise.
(SET_TFHAR): Likewise.
(SET_TFIAR): Likewise.
* config/rs6000/rs6000-call.c (rs6000_expand_new_builtin): Handle
bif_is_32bit and bif_is_endian cases.
(rs6000_init_builtins): Vector pair and vector quad should not be
guarded by TARGET_EXTRA_BUILTINS.
* config/rs6000/rs6000-gen-builtins.c (attrinfo): Add is32bit and
isendian.
(parse_bif_attrs): Handle is32bit and isendian.
(write_decls): Likewise.
(write_bif_static_init): Likewise.
* config/rs6000/rs6000-overload.def (VBPERMQ_VUQ): VBPERMQ, not
VBPERMD.
gcc/testsuite/
* gcc.target/powerpc/bfp/scalar-extract-exp-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Adjust.
* gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Adjust.
* gcc.target/powerpc/bfp/scalar-insert-exp-8.c: Adjust.
* gcc.target/powerpc/byte-in-set-2.c: Adjust.
* gcc.target/powerpc/p8vector-builtin-8.c: Adjust.
* gcc.target/powerpc/test_mffsl.c: Adjust.
* gcc.target/powerpc/vsu/vec-xl-len-13.c: Adjust.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 48 +++++------
gcc/config/rs6000/rs6000-call.c | 93 +++++++++++++++-------
gcc/config/rs6000/rs6000-gen-builtins.c | 43 +++++++---
gcc/config/rs6000/rs6000-overload.def | 2 +-
.../gcc.target/powerpc/bfp/scalar-extract-exp-2.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-extract-sig-2.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-insert-exp-2.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-insert-exp-5.c | 2 +-
.../gcc.target/powerpc/bfp/scalar-insert-exp-8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c | 2 +-
.../gcc.target/powerpc/p8vector-builtin-8.c | 4 +-
gcc/testsuite/gcc.target/powerpc/test_mffsl.c | 3 +-
.../gcc.target/powerpc/vsu/vec-xl-len-13.c | 2 +-
13 files changed, 133 insertions(+), 74 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 79947af74be..55e808c4672 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -126,10 +126,12 @@
; quad MMA instruction using a register quad as an input operand
; pair MMA instruction using a register pair as an input operand
; no32bit Not valid for TARGET_32BIT
+; 32bit Requires different handling for TARGET_32BIT
; cpu This is a "cpu_is" or "cpu_supports" builtin
; ldstmask Altivec mask for load or store
; lxvrse Needs special handling for load-rightmost, sign-extended
; lxvrze Needs special handling for load-rightmost, zero-extended
+; endian Needs special handling for endianness
;
; Each attribute corresponds to extra processing required when
; the built-in is expanded. All such special processing should
@@ -206,7 +208,7 @@
; expanded to rs6000_mftb_di in 64-bit mode, and rs6000_mftb_si in
; 32-bit mode. Use of "long" for this builtin is sanctioned.
unsigned long __builtin_ppc_mftb ();
- MFTB rs6000_mftb_di {}
+ MFTB rs6000_mftb_di {32bit}
void __builtin_mtfsb0 (const int<5>);
MTFSB0 rs6000_mtfsb0 {}
@@ -1390,25 +1392,25 @@
FLOATO_V2DI floatov2di {}
pure vsq __builtin_vsx_ld_elemrev_v1ti (signed long, const void *);
- LD_ELEMREV_V1TI vsx_ld_elemrev_v1ti {ldvec}
+ LD_ELEMREV_V1TI vsx_ld_elemrev_v1ti {ldvec,endian}
pure vd __builtin_vsx_ld_elemrev_v2df (signed long, const void *);
- LD_ELEMREV_V2DF vsx_ld_elemrev_v2df {ldvec}
+ LD_ELEMREV_V2DF vsx_ld_elemrev_v2df {ldvec,endian}
pure vsll __builtin_vsx_ld_elemrev_v2di (signed long, const void *);
- LD_ELEMREV_V2DI vsx_ld_elemrev_v2di {ldvec}
+ LD_ELEMREV_V2DI vsx_ld_elemrev_v2di {ldvec,endian}
pure vf __builtin_vsx_ld_elemrev_v4sf (signed long, const void *);
- LD_ELEMREV_V4SF vsx_ld_elemrev_v4sf {ldvec}
+ LD_ELEMREV_V4SF vsx_ld_elemrev_v4sf {ldvec,endian}
pure vsi __builtin_vsx_ld_elemrev_v4si (signed long, const void *);
- LD_ELEMREV_V4SI vsx_ld_elemrev_v4si {ldvec}
+ LD_ELEMREV_V4SI vsx_ld_elemrev_v4si {ldvec,endian}
pure vss __builtin_vsx_ld_elemrev_v8hi (signed long, const void *);
- LD_ELEMREV_V8HI vsx_ld_elemrev_v8hi {ldvec}
+ LD_ELEMREV_V8HI vsx_ld_elemrev_v8hi {ldvec,endian}
pure vsc __builtin_vsx_ld_elemrev_v16qi (signed long, const void *);
- LD_ELEMREV_V16QI vsx_ld_elemrev_v16qi {ldvec}
+ LD_ELEMREV_V16QI vsx_ld_elemrev_v16qi {ldvec,endian}
; There is apparent intent in rs6000-builtin.def to have RS6000_BTC_SPECIAL
; processing for LXSDX, LXVDSX, and STXSDX, but there are no def_builtin calls
@@ -1476,25 +1478,25 @@
SPLAT_2DI_UNS vsx_splat_v2di {}
void __builtin_vsx_st_elemrev_v1ti (vsq, signed long, void *);
- ST_ELEMREV_V1TI vsx_st_elemrev_v1ti {stvec}
+ ST_ELEMREV_V1TI vsx_st_elemrev_v1ti {stvec,endian}
void __builtin_vsx_st_elemrev_v2df (vd, signed long, void *);
- ST_ELEMREV_V2DF vsx_st_elemrev_v2df {stvec}
+ ST_ELEMREV_V2DF vsx_st_elemrev_v2df {stvec,endian}
void __builtin_vsx_st_elemrev_v2di (vsll, signed long, void *);
- ST_ELEMREV_V2DI vsx_st_elemrev_v2di {stvec}
+ ST_ELEMREV_V2DI vsx_st_elemrev_v2di {stvec,endian}
void __builtin_vsx_st_elemrev_v4sf (vf, signed long, void *);
- ST_ELEMREV_V4SF vsx_st_elemrev_v4sf {stvec}
+ ST_ELEMREV_V4SF vsx_st_elemrev_v4sf {stvec,endian}
void __builtin_vsx_st_elemrev_v4si (vsi, signed long, void *);
- ST_ELEMREV_V4SI vsx_st_elemrev_v4si {stvec}
+ ST_ELEMREV_V4SI vsx_st_elemrev_v4si {stvec,endian}
void __builtin_vsx_st_elemrev_v8hi (vss, signed long, void *);
- ST_ELEMREV_V8HI vsx_st_elemrev_v8hi {stvec}
+ ST_ELEMREV_V8HI vsx_st_elemrev_v8hi {stvec,endian}
void __builtin_vsx_st_elemrev_v16qi (vsc, signed long, void *);
- ST_ELEMREV_V16QI vsx_st_elemrev_v16qi {stvec}
+ ST_ELEMREV_V16QI vsx_st_elemrev_v16qi {stvec,endian}
void __builtin_vsx_stxvd2x_v1ti (vsq, signed long, void *);
STXVD2X_V1TI vsx_store_v1ti {stvec}
@@ -2991,28 +2993,28 @@
[htm]
- unsigned long long __builtin_get_texasr ();
+ unsigned long __builtin_get_texasr ();
GET_TEXASR nothing {htm,htmspr}
- unsigned long long __builtin_get_texasru ();
+ unsigned long __builtin_get_texasru ();
GET_TEXASRU nothing {htm,htmspr}
- unsigned long long __builtin_get_tfhar ();
+ unsigned long __builtin_get_tfhar ();
GET_TFHAR nothing {htm,htmspr}
- unsigned long long __builtin_get_tfiar ();
+ unsigned long __builtin_get_tfiar ();
GET_TFIAR nothing {htm,htmspr}
- void __builtin_set_texasr (unsigned long long);
+ void __builtin_set_texasr (unsigned long);
SET_TEXASR nothing {htm,htmspr}
- void __builtin_set_texasru (unsigned long long);
+ void __builtin_set_texasru (unsigned long);
SET_TEXASRU nothing {htm,htmspr}
- void __builtin_set_tfhar (unsigned long long);
+ void __builtin_set_tfhar (unsigned long);
SET_TFHAR nothing {htm,htmspr}
- void __builtin_set_tfiar (unsigned long long);
+ void __builtin_set_tfiar (unsigned long);
SET_TFIAR nothing {htm,htmspr}
unsigned int __builtin_tabort (unsigned int);
diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c
index fa50315e9b3..82f49f8b320 100644
--- a/gcc/config/rs6000/rs6000-call.c
+++ b/gcc/config/rs6000/rs6000-call.c
@@ -15454,6 +15454,48 @@ rs6000_expand_new_builtin (tree exp, rtx target,
if (bif_is_htm (*bifaddr))
return new_htm_expand_builtin (bifaddr, fcode, exp, target);
+ if (bif_is_32bit (*bifaddr) && TARGET_32BIT)
+ {
+ if (fcode == RS6000_BIF_MFTB)
+ icode = CODE_FOR_rs6000_mftb_si;
+ else
+ gcc_unreachable ();
+ }
+
+ if (bif_is_endian (*bifaddr) && BYTES_BIG_ENDIAN)
+ {
+ if (fcode == RS6000_BIF_LD_ELEMREV_V1TI)
+ icode = CODE_FOR_vsx_load_v1ti;
+ else if (fcode == RS6000_BIF_LD_ELEMREV_V2DF)
+ icode = CODE_FOR_vsx_load_v2df;
+ else if (fcode == RS6000_BIF_LD_ELEMREV_V2DI)
+ icode = CODE_FOR_vsx_load_v2di;
+ else if (fcode == RS6000_BIF_LD_ELEMREV_V4SF)
+ icode = CODE_FOR_vsx_load_v4sf;
+ else if (fcode == RS6000_BIF_LD_ELEMREV_V4SI)
+ icode = CODE_FOR_vsx_load_v4si;
+ else if (fcode == RS6000_BIF_LD_ELEMREV_V8HI)
+ icode = CODE_FOR_vsx_load_v8hi;
+ else if (fcode == RS6000_BIF_LD_ELEMREV_V16QI)
+ icode = CODE_FOR_vsx_load_v16qi;
+ else if (fcode == RS6000_BIF_ST_ELEMREV_V1TI)
+ icode = CODE_FOR_vsx_store_v1ti;
+ else if (fcode == RS6000_BIF_ST_ELEMREV_V2DF)
+ icode = CODE_FOR_vsx_store_v2df;
+ else if (fcode == RS6000_BIF_ST_ELEMREV_V2DI)
+ icode = CODE_FOR_vsx_store_v2di;
+ else if (fcode == RS6000_BIF_ST_ELEMREV_V4SF)
+ icode = CODE_FOR_vsx_store_v4sf;
+ else if (fcode == RS6000_BIF_ST_ELEMREV_V4SI)
+ icode = CODE_FOR_vsx_store_v4si;
+ else if (fcode == RS6000_BIF_ST_ELEMREV_V8HI)
+ icode = CODE_FOR_vsx_store_v8hi;
+ else if (fcode == RS6000_BIF_ST_ELEMREV_V16QI)
+ icode = CODE_FOR_vsx_store_v16qi;
+ else
+ gcc_unreachable ();
+ }
+
rtx pat;
const int MAX_BUILTIN_ARGS = 6;
tree arg[MAX_BUILTIN_ARGS];
@@ -15930,34 +15972,31 @@ rs6000_init_builtins (void)
ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
/* Vector pair and vector quad support. */
- if (TARGET_EXTRA_BUILTINS)
- {
- vector_pair_type_node = make_node (OPAQUE_TYPE);
- SET_TYPE_MODE (vector_pair_type_node, OOmode);
- TYPE_SIZE (vector_pair_type_node) = bitsize_int (GET_MODE_BITSIZE (OOmode));
- TYPE_PRECISION (vector_pair_type_node) = GET_MODE_BITSIZE (OOmode);
- TYPE_SIZE_UNIT (vector_pair_type_node) = size_int (GET_MODE_SIZE (OOmode));
- SET_TYPE_ALIGN (vector_pair_type_node, 256);
- TYPE_USER_ALIGN (vector_pair_type_node) = 0;
- lang_hooks.types.register_builtin_type (vector_pair_type_node,
- "__vector_pair");
- ptr_vector_pair_type_node
- = build_pointer_type (build_qualified_type (vector_pair_type_node,
- TYPE_QUAL_CONST));
+ vector_pair_type_node = make_node (OPAQUE_TYPE);
+ SET_TYPE_MODE (vector_pair_type_node, OOmode);
+ TYPE_SIZE (vector_pair_type_node) = bitsize_int (GET_MODE_BITSIZE (OOmode));
+ TYPE_PRECISION (vector_pair_type_node) = GET_MODE_BITSIZE (OOmode);
+ TYPE_SIZE_UNIT (vector_pair_type_node) = size_int (GET_MODE_SIZE (OOmode));
+ SET_TYPE_ALIGN (vector_pair_type_node, 256);
+ TYPE_USER_ALIGN (vector_pair_type_node) = 0;
+ lang_hooks.types.register_builtin_type (vector_pair_type_node,
+ "__vector_pair");
+ ptr_vector_pair_type_node
+ = build_pointer_type (build_qualified_type (vector_pair_type_node,
+ TYPE_QUAL_CONST));
- vector_quad_type_node = make_node (OPAQUE_TYPE);
- SET_TYPE_MODE (vector_quad_type_node, XOmode);
- TYPE_SIZE (vector_quad_type_node) = bitsize_int (GET_MODE_BITSIZE (XOmode));
- TYPE_PRECISION (vector_quad_type_node) = GET_MODE_BITSIZE (XOmode);
- TYPE_SIZE_UNIT (vector_quad_type_node) = size_int (GET_MODE_SIZE (XOmode));
- SET_TYPE_ALIGN (vector_quad_type_node, 512);
- TYPE_USER_ALIGN (vector_quad_type_node) = 0;
- lang_hooks.types.register_builtin_type (vector_quad_type_node,
- "__vector_quad");
- ptr_vector_quad_type_node
- = build_pointer_type (build_qualified_type (vector_quad_type_node,
- TYPE_QUAL_CONST));
- }
+ vector_quad_type_node = make_node (OPAQUE_TYPE);
+ SET_TYPE_MODE (vector_quad_type_node, XOmode);
+ TYPE_SIZE (vector_quad_type_node) = bitsize_int (GET_MODE_BITSIZE (XOmode));
+ TYPE_PRECISION (vector_quad_type_node) = GET_MODE_BITSIZE (XOmode);
+ TYPE_SIZE_UNIT (vector_quad_type_node) = size_int (GET_MODE_SIZE (XOmode));
+ SET_TYPE_ALIGN (vector_quad_type_node, 512);
+ TYPE_USER_ALIGN (vector_quad_type_node) = 0;
+ lang_hooks.types.register_builtin_type (vector_quad_type_node,
+ "__vector_quad");
+ ptr_vector_quad_type_node
+ = build_pointer_type (build_qualified_type (vector_quad_type_node,
+ TYPE_QUAL_CONST));
/* Initialize the modes for builtin_function_type, mapping a machine mode to
tree type node. */
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index ca1e2098dff..1495929e1e4 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -85,10 +85,12 @@ along with GCC; see the file COPYING3. If not see
quad MMA instruction using a register quad as an input operand
pair MMA instruction using a register pair as an input operand
no32bit Not valid for TARGET_32BIT
+ 32bit Requires different handling for TARGET_32BIT
cpu This is a "cpu_is" or "cpu_supports" builtin
ldstmask Altivec mask for load or store
lxvrse Needs special handling for load-rightmost, sign-extended
lxvrze Needs special handling for load-rightmost, zero-extended
+ endian Needs special handling for endianness
An example stanza might look like this:
@@ -363,10 +365,12 @@ struct attrinfo {
char isquad;
char ispair;
char isno32bit;
+ char is32bit;
char iscpu;
char isldstmask;
char islxvrse;
char islxvrze;
+ char isendian;
};
/* Fields associated with a function prototype (bif or overload). */
@@ -1350,6 +1354,8 @@ parse_bif_attrs (attrinfo *attrptr)
attrptr->ispair = 1;
else if (!strcmp (attrname, "no32bit"))
attrptr->isno32bit = 1;
+ else if (!strcmp (attrname, "32bit"))
+ attrptr->is32bit = 1;
else if (!strcmp (attrname, "cpu"))
attrptr->iscpu = 1;
else if (!strcmp (attrname, "ldstmask"))
@@ -1358,6 +1364,8 @@ parse_bif_attrs (attrinfo *attrptr)
attrptr->islxvrse = 1;
else if (!strcmp (attrname, "lxvrze"))
attrptr->islxvrze = 1;
+ else if (!strcmp (attrname, "endian"))
+ attrptr->isendian = 1;
else
{
(*diag) ("unknown attribute at column %d.\n", oldpos + 1);
@@ -1390,13 +1398,15 @@ parse_bif_attrs (attrinfo *attrptr)
(*diag) ("attribute set: init = %d, set = %d, extract = %d, \
nosoft = %d, ldvec = %d, stvec = %d, reve = %d, pred = %d, htm = %d, \
htmspr = %d, htmcr = %d, mma = %d, quad = %d, pair = %d, no32bit = %d, \
-cpu = %d, ldstmask = %d, lxvrse = %d, lxvrze = %d.\n",
+32bit = %d, cpu = %d, ldstmask = %d, lxvrse = %d, lxvrze = %d, \
+endian = %d.\n",
attrptr->isinit, attrptr->isset, attrptr->isextract,
attrptr->isnosoft, attrptr->isldvec, attrptr->isstvec,
attrptr->isreve, attrptr->ispred, attrptr->ishtm, attrptr->ishtmspr,
attrptr->ishtmcr, attrptr->ismma, attrptr->isquad, attrptr->ispair,
- attrptr->isno32bit, attrptr->iscpu, attrptr->isldstmask,
- attrptr->islxvrse, attrptr->islxvrze);
+ attrptr->isno32bit, attrptr->is32bit, attrptr->iscpu,
+ attrptr->isldstmask, attrptr->islxvrse, attrptr->islxvrze,
+ attrptr->isendian);
#endif
return PC_OK;
@@ -2208,10 +2218,12 @@ write_decls ()
fprintf (header_file, "#define bif_quad_bit\t\t(0x00001000)\n");
fprintf (header_file, "#define bif_pair_bit\t\t(0x00002000)\n");
fprintf (header_file, "#define bif_no32bit_bit\t\t(0x00004000)\n");
- fprintf (header_file, "#define bif_cpu_bit\t\t(0x00008000)\n");
- fprintf (header_file, "#define bif_ldstmask_bit\t(0x00010000)\n");
- fprintf (header_file, "#define bif_lxvrse_bit\t\t(0x00020000)\n");
- fprintf (header_file, "#define bif_lxvrze_bit\t\t(0x00040000)\n");
+ fprintf (header_file, "#define bif_32bit_bit\t\t(0x00008000)\n");
+ fprintf (header_file, "#define bif_cpu_bit\t\t(0x00010000)\n");
+ fprintf (header_file, "#define bif_ldstmask_bit\t(0x00020000)\n");
+ fprintf (header_file, "#define bif_lxvrse_bit\t\t(0x00040000)\n");
+ fprintf (header_file, "#define bif_lxvrze_bit\t\t(0x00080000)\n");
+ fprintf (header_file, "#define bif_endian_bit\t\t(0x00100000)\n");
fprintf (header_file, "\n");
fprintf (header_file,
"#define bif_is_init(x)\t\t((x).bifattrs & bif_init_bit)\n");
@@ -2243,17 +2255,18 @@ write_decls ()
"#define bif_is_pair(x)\t\t((x).bifattrs & bif_pair_bit)\n");
fprintf (header_file,
"#define bif_is_no32bit(x)\t((x).bifattrs & bif_no32bit_bit)\n");
+ fprintf (header_file,
+ "#define bif_is_32bit(x)\t((x).bifattrs & bif_32bit_bit)\n");
fprintf (header_file,
"#define bif_is_cpu(x)\t\t((x).bifattrs & bif_cpu_bit)\n");
fprintf (header_file,
- "#define bif_is_ldstmask(x)\t((x).bifattrs "
- "& bif_ldstmask_bit)\n");
+ "#define bif_is_ldstmask(x)\t((x).bifattrs & bif_ldstmask_bit)\n");
+ fprintf (header_file,
+ "#define bif_is_lxvrse(x)\t((x).bifattrs & bif_lxvrse_bit)\n");
fprintf (header_file,
- "#define bif_is_lxvrse(x)\t((x).bifattrs "
- "& bif_lxvrse_bit)\n");
+ "#define bif_is_lxvrze(x)\t((x).bifattrs & bif_lxvrze_bit)\n");
fprintf (header_file,
- "#define bif_is_lxvrze(x)\t((x).bifattrs "
- "& bif_lxvrze_bit)\n");
+ "#define bif_is_endian(x)\t((x).bifattrs & bif_endian_bit)\n");
fprintf (header_file, "\n");
/* #### Note that the _x is added for now to avoid conflict with
@@ -2484,6 +2497,8 @@ write_bif_static_init ()
fprintf (init_file, " | bif_pair_bit");
if (bifp->attrs.isno32bit)
fprintf (init_file, " | bif_no32bit_bit");
+ if (bifp->attrs.is32bit)
+ fprintf (init_file, " | bif_32bit_bit");
if (bifp->attrs.iscpu)
fprintf (init_file, " | bif_cpu_bit");
if (bifp->attrs.isldstmask)
@@ -2492,6 +2507,8 @@ write_bif_static_init ()
fprintf (init_file, " | bif_lxvrse_bit");
if (bifp->attrs.islxvrze)
fprintf (init_file, " | bif_lxvrze_bit");
+ if (bifp->attrs.isendian)
+ fprintf (init_file, " | bif_endian_bit");
fprintf (init_file, ",\n");
fprintf (init_file, " /* restr_opnd */\t{%d, %d, %d},\n",
bifp->proto.restr_opnd[0], bifp->proto.restr_opnd[1],
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 98526d18b6d..0ac1d4edd64 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -536,7 +536,7 @@
vull __builtin_vec_vbperm_api (vull, vuc);
VBPERMD VBPERMD_VULL
vull __builtin_vec_vbperm_api (vuq, vuc);
- VBPERMD VBPERMD_VUQ
+ VBPERMQ VBPERMQ_VUQ
vuc __builtin_vec_vbperm_api (vuc, vuc);
VBPERMQ2 VBPERMQ2_U
vsc __builtin_vec_vbperm_api (vsc, vsc);
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c
index 922180675fc..53b67c95cf9 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c
@@ -14,7 +14,7 @@ get_exponent (double *p)
{
double source = *p;
- return scalar_extract_exp (source); /* { dg-error "'__builtin_vec_scalar_extract_exp' is not supported in this compiler configuration" } */
+ return scalar_extract_exp (source); /* { dg-error "'__builtin_vsx_scalar_extract_exp' requires the" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c
index e24d4bd23fe..39ee74c94dc 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-2.c
@@ -12,5 +12,5 @@ get_significand (double *p)
{
double source = *p;
- return __builtin_vec_scalar_extract_sig (source); /* { dg-error "'__builtin_vec_scalar_extract_sig' is not supported in this compiler configuration" } */
+ return __builtin_vec_scalar_extract_sig (source); /* { dg-error "'__builtin_vsx_scalar_extract_sig' requires the" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c
index feb943104da..efd69725905 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-2.c
@@ -16,5 +16,5 @@ insert_exponent (unsigned long long int *significand_p,
unsigned long long int significand = *significand_p;
unsigned long long int exponent = *exponent_p;
- return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vec_scalar_insert_exp' is not supported in this compiler configuration" } */
+ return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vsx_scalar_insert_exp' requires the" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c
index 0e5683d5d1a..f85966a6fdf 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-5.c
@@ -16,5 +16,5 @@ insert_exponent (double *significand_p,
double significand = *significand_p;
unsigned long long int exponent = *exponent_p;
- return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vec_scalar_insert_exp' is not supported in this compiler configuration" } */
+ return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vsx_scalar_insert_exp_dp' requires the" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c
index bd68f770985..b1be8284b4e 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-8.c
@@ -16,5 +16,5 @@ insert_exponent (unsigned __int128 *significand_p, /* { dg-error "'__int128' is
unsigned __int128 significand = *significand_p; /* { dg-error "'__int128' is not supported on this target" } */
unsigned long long int exponent = *exponent_p;
- return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vec_scalar_insert_exp' is not supported in this compiler configuration" } */
+ return scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vsx_scalar_insert_exp' requires the" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c b/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c
index 44cc7782760..4c676ba356d 100644
--- a/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/byte-in-set-2.c
@@ -10,5 +10,5 @@
int
test_byte_in_set (unsigned char b, unsigned long long set_members)
{
- return __builtin_byte_in_set (b, set_members); /* { dg-warning "implicit declaration of function" } */
+ return __builtin_byte_in_set (b, set_members); /* { dg-error "'__builtin_scalar_byte_in_set' requires the" } */
}
diff --git a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
index b109fcdb93c..1d09aad9fbf 100644
--- a/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
+++ b/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-8.c
@@ -125,8 +125,8 @@ void foo (vector signed char *vscr,
/* { dg-final { scan-assembler-times "vsubecuq" 2 } } */
/* { dg-final { scan-assembler-times "vsubcuw" 4 } } */
/* { dg-final { scan-assembler-times "vsubuwm" 4 } } */
-/* { dg-final { scan-assembler-times "vbpermq" 1 } } */
-/* { dg-final { scan-assembler-times "vbpermd" 1 } } */
+/* { dg-final { scan-assembler-times "vbpermq" 2 } } */
+/* { dg-final { scan-assembler-times "vbpermd" 0 } } */
/* { dg-final { scan-assembler-times "xxleqv" 4 } } */
/* { dg-final { scan-assembler-times "vgbbd" 1 } } */
/* { dg-final { scan-assembler-times "xxlnand" 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/test_mffsl.c b/gcc/testsuite/gcc.target/powerpc/test_mffsl.c
index 41377efba1a..28c2b91988e 100644
--- a/gcc/testsuite/gcc.target/powerpc/test_mffsl.c
+++ b/gcc/testsuite/gcc.target/powerpc/test_mffsl.c
@@ -1,5 +1,6 @@
/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-options "-O2 -std=c99" } */
+/* { dg-options "-O2 -std=c99 -mcpu=power9" } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
#ifdef DEBUG
#include <stdio.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c
index 1cfed57d6a6..0f601fbbb50 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c
@@ -13,5 +13,5 @@
int
fetch_data (float *address, size_t length)
{
- return __builtin_vec_lxvl (address, length); /* { dg-warning "'__builtin_vec_lxvl'" } */
+ return __builtin_vec_lxvl (address, length); /* { dg-error "'__builtin_vsx_lxvl' requires the" } */
}
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