[gcc r10-9506] PR target/99702: Check RTL type before get value

[Kito Cheng]

https://gcc.gnu.org/g:e1aa525179b72fb7ea7822c794ec844893ed47e4

commit r10-9506-ge1aa525179b72fb7ea7822c794ec844893ed47e4
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Mon Mar 22 16:32:45 2021 +0800

    PR target/99702: Check RTL type before get value
    
    gcc/ChangeLog:
    
            PR target/99702
            * config/riscv/riscv.c (riscv_expand_block_move): Get RTL value
            after type checking.
    
    gcc/testsuite/ChangeLog:
    
            PR target/99702
            * gcc.target/riscv/pr99702.c: New.
    
    (cherry picked from commit 540dace2ed3949571f2ce6cb007354e69bda0cb2)

Diff:
---
 gcc/config/riscv/riscv.c                 | 2 +-
 gcc/testsuite/gcc.target/riscv/pr99702.c | 7 +++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index a08a9256d73..2718abb2004 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -3152,9 +3152,9 @@ riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length,
 bool
 riscv_expand_block_move (rtx dest, rtx src, rtx length)
 {
-  unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
   if (CONST_INT_P (length))
     {
+      unsigned HOST_WIDE_INT hwi_length = UINTVAL (length);
       unsigned HOST_WIDE_INT factor, align;
 
       align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD);
diff --git a/gcc/testsuite/gcc.target/riscv/pr99702.c b/gcc/testsuite/gcc.target/riscv/pr99702.c
new file mode 100644
index 00000000000..a28724c0958
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr99702.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+char n;
+void *i, *j;
+void foo(void) {
+  __builtin_memcpy(i, j, n);
+}