[gcc(refs/users/meissner/heads/work042)] Generate XXSPLTIW for V8HI constants.

[Michael Meissner]

https://gcc.gnu.org/g:73763015752c0d9f6a889addd91fcf8165ae4a4b

commit 73763015752c0d9f6a889addd91fcf8165ae4a4b
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Mar 19 13:35:00 2021 -0400

    Generate XXSPLTIW for V8HI constants.
    
    This code adds support for using XXSPLTIW to generate vector short
    constants.
    
    gcc/
    2021-03-19  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/altivec.md (xxspltiw_v8hi): New insn.
            * config/rs6000/rs6000.c (xxspltiw_constant_p): Add support for
            V8HImode constants.
            (output_vec_const_move): Add support for V8HImode constants.
            (rs6000_expand_vector_init): Use VEC_DUPLICATE for identical
            vector V8HI constants.

Diff:
---
 gcc/config/rs6000/altivec.md | 28 +++++++++++++++++++++++++++-
 gcc/config/rs6000/rs6000.c   | 35 +++++++++++++++++++++++++++++------
 2 files changed, 56 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 2fb22172bec..e239104f249 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -819,7 +819,33 @@
   "vs<SLDB_lr>dbi %0,%1,%2,%3"
   [(set_attr "type" "vecsimple")])
 
-;; Generate VSPLTIW, XXSPLITB, or XXSPLTIW to load up V4SI constants.
+;; Generate VSPLTIW, XXSPLITB, or XXSPLTIW to load up V4SI/V8HI/V4SF constants.
+(define_insn "*xxspltiw_v8hi"
+  [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa,wa,v,wa")
+       (vec_duplicate:V8HI
+        (match_operand 1 "short_cint_operand" "O,wM,wB,n")))]
+ "TARGET_POWER10"
+{
+  int value = INTVAL (operands[1]);
+
+  if (value == 0)
+    return "xxspltib %x0,0";
+
+  else if (value == -1)
+    return "xxspltib %x0,255";
+
+  int r = reg_or_subregno (operands[0]);
+  if (IN_RANGE (value, -16, 15) && ALTIVEC_REGNO_P (r))
+    return "vspltish %0,%1";
+
+  int tmp = value & 0xffff;
+  operands[2] = GEN_INT ((tmp << 16) | tmp);
+  return "xxspltiw %x0,%2";
+}
+ [(set_attr "type" "vecperm")
+  (set_attr "prefixed" "*,*,*,yes")
+  (set_attr "prefixed_prepend_p" "*,*,*,no")])
+
 (define_insn "xxspltiw_v4si"
   [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa,v,wa")
        (vec_duplicate:V4SI
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 33d084efd93..209f3c786fd 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6338,7 +6338,7 @@ xxspltiw_constant_p (rtx op, machine_mode mode, rtx *constant_ptr)
   else if (mode != GET_MODE (op))
     return false;
 
-  if (mode != V4SImode || mode != V4SFmode)
+  if (mode != V4SImode && mode != V4SFmode && mode != V8HImode)
     return false;
 
   rtx element;
@@ -6547,11 +6547,33 @@ output_vec_const_move (rtx *operands)
 	    gcc_unreachable ();
 
 	  HOST_WIDE_INT value = INTVAL (operands[2]);
-	  if (IN_RANGE (value, -16, 15) && dest_vmx_p && mode == V4SImode)
-	    return "vspltisw %0,%2";
+	  HOST_WIDE_INT tmp;
+	  switch (mode)
+	    {
+	    case E_V16QImode:
+	      operands[2] = GEN_INT (value & 0xff);
+	      return "xxspltib %x0,%2";
 
-	  else
-	    return "xxspltiw %x0,%2";
+	    case E_V8HImode:
+	      if (IN_RANGE (value, -16, 15) && dest_vmx_p)
+		return "vspltish %0,%2";
+
+	      tmp = value & 0xffff;
+	      operands[2] = GEN_INT ((tmp << 16) | tmp);
+	      return "xxspltiw %x0,%2";
+
+	    case E_V4SImode:
+	      if (IN_RANGE (value, -16, 15) && dest_vmx_p)
+		return "vspltisw %0,%2";
+
+	      return "xxspltiw %x0,%2";
+
+	    case E_V4SFmode:
+	      return "xxspltiw %x0,%2";
+
+	    default:
+	      break;
+	    }
 	}
 
       if (TARGET_P9_VECTOR
@@ -6636,7 +6658,8 @@ rs6000_expand_vector_init (rtx target, rtx vals)
   if (n_var == 0)
     {
       /* Generate XXSPLTIW if we can.  */
-      if (TARGET_POWER10 && all_same && (mode == V4SImode || mode == V4SFmode))
+      if (TARGET_POWER10 && all_same
+	  && (mode == V4SImode || mode == V4SFmode || mode == V8HImode))
 	{
 	  rtx dup = gen_rtx_VEC_DUPLICATE (mode, XVECEXP (vals, 0, 0));
 	  emit_insn (gen_rtx_SET (target, dup));