[gcc(refs/users/meissner/heads/work041)] Generate XXSPLTIW for vector float constants.

[Michael Meissner]

https://gcc.gnu.org/g:ffd0f63556e8af470ef111bd8d1737dc68cc54f9

commit ffd0f63556e8af470ef111bd8d1737dc68cc54f9
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Mar 12 02:00:06 2021 -0500

    Generate XXSPLTIW for vector float constants.
    
    This patch extends the vector support to use XXSPLTIW for generating
    V4SFmode constants.
    
    gcc/
    2021-03-12  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/altivec.md (UNSPEC_XXSPLTIW): Delete.
            (xxspltiw_v4sf): Rewrite to use VEC_DUPLICATE.
            (xxspltiw_v4sf_inst): Delete.
            * config/rs6000/rs6000.c (rs6000_expand_vector_init): Use XXSPLTIW
            to load vector float constants that are all the same.

Diff:
---
 gcc/config/rs6000/altivec.md | 28 +++++++++++-----------------
 gcc/config/rs6000/rs6000.c   |  3 ++-
 2 files changed, 13 insertions(+), 18 deletions(-)

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 66b8d508e01..e90acaf1f80 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -176,7 +176,6 @@
    UNSPEC_VSTRIL
    UNSPEC_SLDB
    UNSPEC_SRDB
-   UNSPEC_XXSPLTIW
    UNSPEC_XXSPLTID
    UNSPEC_XXSPLTI32DX
    UNSPEC_XXBLEND
@@ -835,26 +834,21 @@
   (set_attr "prefixed" "*,*,*,yes")
   (set_attr "prefixed_prepend_p" "*,*,*,no")])
 
-(define_expand "xxspltiw_v4sf"
-  [(set (match_operand:V4SF 0 "register_operand" "=wa")
-	(unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")]
-		     UNSPEC_XXSPLTIW))]
+(define_insn "xxspltiw_v4sf"
+  [(set (match_operand:V4SF 0 "register_operand" "=wa,wa")
+	(vec_duplicate:V4SF
+	 (match_operand:SF 1 "const_double_operand" "j,n")))]
  "TARGET_POWER10"
 {
-  long long value = rs6000_const_f32_to_i32 (operands[1]);
-  emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value)));
-  DONE;
-})
+  if (operands[1] == CONST0_RTX (SFmode))
+    return "xxspltib %x0,0";
 
-(define_insn "xxspltiw_v4sf_inst"
-  [(set (match_operand:V4SF 0 "register_operand" "=wa")
-	(unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
-		     UNSPEC_XXSPLTIW))]
- "TARGET_POWER10"
- "xxspltiw %x0,%1"
+  operands[2] = GEN_INT (rs6000_const_f32_to_i32 (operands[1]));
+  return "xxspltiw %x0,%2";
+}
  [(set_attr "type" "vecsimple")
-  (set_attr "prefixed" "yes")
-  (set_attr "prefixed_prepend_p" "no")])
+  (set_attr "prefixed" "*,yes")
+  (set_attr "prefixed_prepend_p" "*,no")])
 
 (define_expand "xxspltidp_v2df"
   [(set (match_operand:V2DF 0 "register_operand" )
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d9f84836daf..ec2c0dc2f7c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6652,7 +6652,8 @@ rs6000_expand_vector_init (rtx target, rtx vals)
   if (n_var == 0)
     {
       /* Generate XXSPLTIW if we can.  */
-      if (TARGET_POWER10 && all_same && mode == V4SImode)
+      if (TARGET_POWER10 && all_same
+	  && (mode == V4SImode || mode == V4SFmode))
 	{
 	  rtx dup = gen_rtx_VEC_DUPLICATE (mode, XVECEXP (vals, 0, 0));
 	  emit_insn (gen_rtx_SET (target, dup));