[gcc(refs/users/acsawdey/heads/fusion-combine)] Add insn types for fusion pairs
Aaron Sawdey
acsawdey@gcc.gnu.org
Fri Mar 5 18:14:06 GMT 2021
https://gcc.gnu.org/g:1f07bb4197ec0317a8141b811f2a67ea1dcfd826
commit 1f07bb4197ec0317a8141b811f2a67ea1dcfd826
Author: Aaron Sawdey <acsawdey@linux.ibm.com>
Date: Tue Mar 2 17:50:52 2021 -0600
Add insn types for fusion pairs
This adds new values for insn attr type for p10 fusion. The genfusion.pl
script is modified to use them, and fusion.md regenerated to capture
the new patterns. There are also some formatting only changes to
fusion.md that apparently weren't captured after a previous commit
of genfusion.pl.
gcc/
* rs6000.md (define_attr "type): Add types for fusion.
* genfusion.md (gen_ld_cmpi_p10): Use new fusion types.
(gen_2logical): Use new fusion types.
* fusion.md: Regenerate.
Diff:
---
gcc/config/rs6000/fusion.md | 451 ++++++++++++++++++++---------------------
gcc/config/rs6000/genfusion.pl | 8 +-
gcc/config/rs6000/rs6000.md | 4 +-
3 files changed, 233 insertions(+), 230 deletions(-)
diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md
index 737a6da385f..74d321d0f5f 100644
--- a/gcc/config/rs6000/fusion.md
+++ b/gcc/config/rs6000/fusion.md
@@ -1,7 +1,6 @@
-;; -*- buffer-read-only: t -*-
;; Generated automatically by genfusion.pl
-;; Copyright (C) 2020 Free Software Foundation, Inc.
+;; Copyright (C) 2020,2021 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
@@ -24,19 +23,19 @@
(define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
(compare:CC (match_operand:DI 1 "non_update_memory_operand" "m")
- (match_operand:DI 3 "const_m1_to_1_operand" "n")))
+ (match_operand:DI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "ld%X1 %0,%1\;cmpdi 0,%0,%3"
+ "ld%X1 %0,%1\;cmpdi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ DImode, NON_PREFIXED_DS))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2)
- (compare:CC (match_dup 0)
- (match_dup 3)))]
+ (compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -45,19 +44,19 @@
(define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
(compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "m")
- (match_operand:DI 3 "const_0_to_1_operand" "n")))
+ (match_operand:DI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:DI 0 "=r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "ld%X1 %0,%1\;cmpldi 0,%0,%3"
+ "ld%X1 %0,%1\;cmpldi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ DImode, NON_PREFIXED_DS))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2)
- (compare:CCUNS (match_dup 0)
- (match_dup 3)))]
+ (compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -66,19 +65,19 @@
(define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
(compare:CC (match_operand:DI 1 "non_update_memory_operand" "m")
- (match_operand:DI 3 "const_m1_to_1_operand" "n")))
+ (match_operand:DI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "ld%X1 %0,%1\;cmpdi 0,%0,%3"
+ "ld%X1 %0,%1\;cmpdi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ DImode, NON_PREFIXED_DS))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2)
- (compare:CC (match_dup 0)
- (match_dup 3)))]
+ (compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -87,19 +86,19 @@
(define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
(compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "m")
- (match_operand:DI 3 "const_0_to_1_operand" "n")))
+ (match_operand:DI 3 "const_0_to_1_operand" "n")))
(set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "ld%X1 %0,%1\;cmpldi 0,%0,%3"
+ "ld%X1 %0,%1\;cmpldi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), DImode, NON_PREFIXED_DS))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ DImode, NON_PREFIXED_DS))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2)
- (compare:CCUNS (match_dup 0)
- (match_dup 3)))]
+ (compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -108,19 +107,19 @@
(define_insn_and_split "*lwa_cmpdi_cr0_SI_clobber_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
(compare:CC (match_operand:SI 1 "non_update_memory_operand" "m")
- (match_operand:SI 3 "const_m1_to_1_operand" "n")))
+ (match_operand:SI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lwa%X1 %0,%1\;cmpdi 0,%0,%3"
+ "lwa%X1 %0,%1\;cmpdi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_DS))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ SImode, NON_PREFIXED_DS))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2)
- (compare:CC (match_dup 0)
- (match_dup 3)))]
+ (compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -129,19 +128,19 @@
(define_insn_and_split "*lwz_cmpldi_cr0_SI_clobber_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
(compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m")
- (match_operand:SI 3 "const_0_to_1_operand" "n")))
+ (match_operand:SI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:SI 0 "=r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lwz%X1 %0,%1\;cmpldi 0,%0,%3"
+ "lwz%X1 %0,%1\;cmpldi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_D))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ SImode, NON_PREFIXED_D))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2)
- (compare:CCUNS (match_dup 0)
- (match_dup 3)))]
+ (compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -150,19 +149,19 @@
(define_insn_and_split "*lwa_cmpdi_cr0_SI_SI_CC_none"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
(compare:CC (match_operand:SI 1 "non_update_memory_operand" "m")
- (match_operand:SI 3 "const_m1_to_1_operand" "n")))
+ (match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lwa%X1 %0,%1\;cmpdi 0,%0,%3"
+ "lwa%X1 %0,%1\;cmpdi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_DS))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ SImode, NON_PREFIXED_DS))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2)
- (compare:CC (match_dup 0)
- (match_dup 3)))]
+ (compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -171,19 +170,19 @@
(define_insn_and_split "*lwz_cmpldi_cr0_SI_SI_CCUNS_none"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
(compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m")
- (match_operand:SI 3 "const_0_to_1_operand" "n")))
+ (match_operand:SI 3 "const_0_to_1_operand" "n")))
(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lwz%X1 %0,%1\;cmpldi 0,%0,%3"
+ "lwz%X1 %0,%1\;cmpldi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_D))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ SImode, NON_PREFIXED_D))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2)
- (compare:CCUNS (match_dup 0)
- (match_dup 3)))]
+ (compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -192,19 +191,19 @@
(define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
(compare:CC (match_operand:SI 1 "non_update_memory_operand" "m")
- (match_operand:SI 3 "const_m1_to_1_operand" "n")))
+ (match_operand:SI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lwa%X1 %0,%1\;cmpdi 0,%0,%3"
+ "lwa%X1 %0,%1\;cmpdi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_DS))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ SImode, NON_PREFIXED_DS))"
[(set (match_dup 0) (sign_extend:EXTSI (match_dup 1)))
(set (match_dup 2)
- (compare:CC (match_dup 0)
- (match_dup 3)))]
+ (compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -213,19 +212,19 @@
(define_insn_and_split "*lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
(compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m")
- (match_operand:SI 3 "const_0_to_1_operand" "n")))
+ (match_operand:SI 3 "const_0_to_1_operand" "n")))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (zero_extend:EXTSI (match_dup 1)))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lwz%X1 %0,%1\;cmpldi 0,%0,%3"
+ "lwz%X1 %0,%1\;cmpldi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), SImode, NON_PREFIXED_D))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ SImode, NON_PREFIXED_D))"
[(set (match_dup 0) (zero_extend:EXTSI (match_dup 1)))
(set (match_dup 2)
- (compare:CCUNS (match_dup 0)
- (match_dup 3)))]
+ (compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -234,19 +233,19 @@
(define_insn_and_split "*lha_cmpdi_cr0_HI_clobber_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
(compare:CC (match_operand:HI 1 "non_update_memory_operand" "m")
- (match_operand:HI 3 "const_m1_to_1_operand" "n")))
+ (match_operand:HI 3 "const_m1_to_1_operand" "n")))
(clobber (match_scratch:GPR 0 "=r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lha%X1 %0,%1\;cmpdi 0,%0,%3"
+ "lha%X1 %0,%1\;cmpdi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), HImode, NON_PREFIXED_D))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ HImode, NON_PREFIXED_D))"
[(set (match_dup 0) (sign_extend:GPR (match_dup 1)))
(set (match_dup 2)
- (compare:CC (match_dup 0)
- (match_dup 3)))]
+ (compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -255,19 +254,19 @@
(define_insn_and_split "*lhz_cmpldi_cr0_HI_clobber_CCUNS_zero"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
(compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m")
- (match_operand:HI 3 "const_0_to_1_operand" "n")))
+ (match_operand:HI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:GPR 0 "=r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lhz%X1 %0,%1\;cmpldi 0,%0,%3"
+ "lhz%X1 %0,%1\;cmpldi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), HImode, NON_PREFIXED_D))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ HImode, NON_PREFIXED_D))"
[(set (match_dup 0) (zero_extend:GPR (match_dup 1)))
(set (match_dup 2)
- (compare:CCUNS (match_dup 0)
- (match_dup 3)))]
+ (compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -276,19 +275,19 @@
(define_insn_and_split "*lha_cmpdi_cr0_HI_EXTHI_CC_sign"
[(set (match_operand:CC 2 "cc_reg_operand" "=x")
(compare:CC (match_operand:HI 1 "non_update_memory_operand" "m")
- (match_operand:HI 3 "const_m1_to_1_operand" "n")))
+ (match_operand:HI 3 "const_m1_to_1_operand" "n")))
(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (sign_extend:EXTHI (match_dup 1)))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lha%X1 %0,%1\;cmpdi 0,%0,%3"
+ "lha%X1 %0,%1\;cmpdi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), HImode, NON_PREFIXED_D))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ HImode, NON_PREFIXED_D))"
[(set (match_dup 0) (sign_extend:EXTHI (match_dup 1)))
(set (match_dup 2)
- (compare:CC (match_dup 0)
- (match_dup 3)))]
+ (compare:CC (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -297,19 +296,19 @@
(define_insn_and_split "*lhz_cmpldi_cr0_HI_EXTHI_CCUNS_zero"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
(compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m")
- (match_operand:HI 3 "const_0_to_1_operand" "n")))
+ (match_operand:HI 3 "const_0_to_1_operand" "n")))
(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (zero_extend:EXTHI (match_dup 1)))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lhz%X1 %0,%1\;cmpldi 0,%0,%3"
+ "lhz%X1 %0,%1\;cmpldi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), HImode, NON_PREFIXED_D))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ HImode, NON_PREFIXED_D))"
[(set (match_dup 0) (zero_extend:EXTHI (match_dup 1)))
(set (match_dup 2)
- (compare:CCUNS (match_dup 0)
- (match_dup 3)))]
+ (compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -318,19 +317,19 @@
(define_insn_and_split "*lbz_cmpldi_cr0_QI_clobber_CCUNS_zero"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
(compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m")
- (match_operand:QI 3 "const_0_to_1_operand" "n")))
+ (match_operand:QI 3 "const_0_to_1_operand" "n")))
(clobber (match_scratch:GPR 0 "=r"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lbz%X1 %0,%1\;cmpldi 0,%0,%3"
+ "lbz%X1 %0,%1\;cmpldi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), QImode, NON_PREFIXED_D))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ QImode, NON_PREFIXED_D))"
[(set (match_dup 0) (zero_extend:GPR (match_dup 1)))
(set (match_dup 2)
- (compare:CCUNS (match_dup 0)
- (match_dup 3)))]
+ (compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -339,19 +338,19 @@
(define_insn_and_split "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero"
[(set (match_operand:CCUNS 2 "cc_reg_operand" "=x")
(compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m")
- (match_operand:QI 3 "const_0_to_1_operand" "n")))
+ (match_operand:QI 3 "const_0_to_1_operand" "n")))
(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (zero_extend:GPR (match_dup 1)))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)"
- "lbz%X1 %0,%1\;cmpldi 0,%0,%3"
+ "lbz%X1 %0,%1\;cmpldi %2,%0,%3"
"&& reload_completed
&& (cc_reg_not_cr0_operand (operands[2], CCmode)
- || !address_is_non_pfx_d_or_x (XEXP (operands[1],0), QImode, NON_PREFIXED_D))"
+ || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0),
+ QImode, NON_PREFIXED_D))"
[(set (match_dup 0) (zero_extend:GPR (match_dup 1)))
(set (match_dup 2)
- (compare:CCUNS (match_dup 0)
- (match_dup 3)))]
+ (compare:CCUNS (match_dup 0) (match_dup 3)))]
""
- [(set_attr "type" "load")
+ [(set_attr "type" "fuse_ldcmpi")
(set_attr "cost" "8")
(set_attr "length" "8")])
@@ -370,7 +369,7 @@
and %3,%1,%0\;and %3,%3,%2
and %3,%1,%0\;and %3,%3,%2
and %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -388,7 +387,7 @@
andc %3,%1,%0\;and %3,%3,%2
andc %3,%1,%0\;and %3,%3,%2
andc %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -406,7 +405,7 @@
eqv %3,%1,%0\;and %3,%3,%2
eqv %3,%1,%0\;and %3,%3,%2
eqv %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -424,7 +423,7 @@
nand %3,%1,%0\;and %3,%3,%2
nand %3,%1,%0\;and %3,%3,%2
nand %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -442,7 +441,7 @@
nor %3,%1,%0\;and %3,%3,%2
nor %3,%1,%0\;and %3,%3,%2
nor %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -460,7 +459,7 @@
or %3,%1,%0\;and %3,%3,%2
or %3,%1,%0\;and %3,%3,%2
or %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -478,7 +477,7 @@
orc %3,%1,%0\;and %3,%3,%2
orc %3,%1,%0\;and %3,%3,%2
orc %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -496,7 +495,7 @@
xor %3,%1,%0\;and %3,%3,%2
xor %3,%1,%0\;and %3,%3,%2
xor %4,%1,%0\;and %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -514,7 +513,7 @@
and %3,%1,%0\;andc %3,%3,%2
and %3,%1,%0\;andc %3,%3,%2
and %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -532,7 +531,7 @@
andc %3,%1,%0\;andc %3,%3,%2
andc %3,%1,%0\;andc %3,%3,%2
andc %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -550,7 +549,7 @@
eqv %3,%1,%0\;andc %3,%3,%2
eqv %3,%1,%0\;andc %3,%3,%2
eqv %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -568,7 +567,7 @@
nand %3,%1,%0\;andc %3,%3,%2
nand %3,%1,%0\;andc %3,%3,%2
nand %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -586,7 +585,7 @@
nor %3,%1,%0\;andc %3,%3,%2
nor %3,%1,%0\;andc %3,%3,%2
nor %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -604,7 +603,7 @@
or %3,%1,%0\;andc %3,%3,%2
or %3,%1,%0\;andc %3,%3,%2
or %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -622,7 +621,7 @@
orc %3,%1,%0\;andc %3,%3,%2
orc %3,%1,%0\;andc %3,%3,%2
orc %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -640,7 +639,7 @@
xor %3,%1,%0\;andc %3,%3,%2
xor %3,%1,%0\;andc %3,%3,%2
xor %4,%1,%0\;andc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -658,7 +657,7 @@
and %3,%1,%0\;eqv %3,%3,%2
and %3,%1,%0\;eqv %3,%3,%2
and %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -676,7 +675,7 @@
andc %3,%1,%0\;eqv %3,%3,%2
andc %3,%1,%0\;eqv %3,%3,%2
andc %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -694,7 +693,7 @@
eqv %3,%1,%0\;eqv %3,%3,%2
eqv %3,%1,%0\;eqv %3,%3,%2
eqv %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -712,7 +711,7 @@
nand %3,%1,%0\;eqv %3,%3,%2
nand %3,%1,%0\;eqv %3,%3,%2
nand %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -730,7 +729,7 @@
nor %3,%1,%0\;eqv %3,%3,%2
nor %3,%1,%0\;eqv %3,%3,%2
nor %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -748,7 +747,7 @@
or %3,%1,%0\;eqv %3,%3,%2
or %3,%1,%0\;eqv %3,%3,%2
or %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -766,7 +765,7 @@
orc %3,%1,%0\;eqv %3,%3,%2
orc %3,%1,%0\;eqv %3,%3,%2
orc %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -784,7 +783,7 @@
xor %3,%1,%0\;eqv %3,%3,%2
xor %3,%1,%0\;eqv %3,%3,%2
xor %4,%1,%0\;eqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -802,7 +801,7 @@
and %3,%1,%0\;nand %3,%3,%2
and %3,%1,%0\;nand %3,%3,%2
and %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -820,7 +819,7 @@
andc %3,%1,%0\;nand %3,%3,%2
andc %3,%1,%0\;nand %3,%3,%2
andc %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -838,7 +837,7 @@
eqv %3,%1,%0\;nand %3,%3,%2
eqv %3,%1,%0\;nand %3,%3,%2
eqv %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -856,7 +855,7 @@
nand %3,%1,%0\;nand %3,%3,%2
nand %3,%1,%0\;nand %3,%3,%2
nand %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -874,7 +873,7 @@
nor %3,%1,%0\;nand %3,%3,%2
nor %3,%1,%0\;nand %3,%3,%2
nor %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -892,7 +891,7 @@
or %3,%1,%0\;nand %3,%3,%2
or %3,%1,%0\;nand %3,%3,%2
or %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -910,7 +909,7 @@
orc %3,%1,%0\;nand %3,%3,%2
orc %3,%1,%0\;nand %3,%3,%2
orc %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -928,7 +927,7 @@
xor %3,%1,%0\;nand %3,%3,%2
xor %3,%1,%0\;nand %3,%3,%2
xor %4,%1,%0\;nand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -946,7 +945,7 @@
and %3,%1,%0\;nor %3,%3,%2
and %3,%1,%0\;nor %3,%3,%2
and %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -964,7 +963,7 @@
andc %3,%1,%0\;nor %3,%3,%2
andc %3,%1,%0\;nor %3,%3,%2
andc %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -982,7 +981,7 @@
eqv %3,%1,%0\;nor %3,%3,%2
eqv %3,%1,%0\;nor %3,%3,%2
eqv %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1000,7 +999,7 @@
nand %3,%1,%0\;nor %3,%3,%2
nand %3,%1,%0\;nor %3,%3,%2
nand %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1018,7 +1017,7 @@
nor %3,%1,%0\;nor %3,%3,%2
nor %3,%1,%0\;nor %3,%3,%2
nor %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1036,7 +1035,7 @@
or %3,%1,%0\;nor %3,%3,%2
or %3,%1,%0\;nor %3,%3,%2
or %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1054,7 +1053,7 @@
orc %3,%1,%0\;nor %3,%3,%2
orc %3,%1,%0\;nor %3,%3,%2
orc %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1072,7 +1071,7 @@
xor %3,%1,%0\;nor %3,%3,%2
xor %3,%1,%0\;nor %3,%3,%2
xor %4,%1,%0\;nor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1090,7 +1089,7 @@
and %3,%1,%0\;or %3,%3,%2
and %3,%1,%0\;or %3,%3,%2
and %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1108,7 +1107,7 @@
andc %3,%1,%0\;or %3,%3,%2
andc %3,%1,%0\;or %3,%3,%2
andc %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1126,7 +1125,7 @@
eqv %3,%1,%0\;or %3,%3,%2
eqv %3,%1,%0\;or %3,%3,%2
eqv %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1144,7 +1143,7 @@
nand %3,%1,%0\;or %3,%3,%2
nand %3,%1,%0\;or %3,%3,%2
nand %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1162,7 +1161,7 @@
nor %3,%1,%0\;or %3,%3,%2
nor %3,%1,%0\;or %3,%3,%2
nor %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1180,7 +1179,7 @@
or %3,%1,%0\;or %3,%3,%2
or %3,%1,%0\;or %3,%3,%2
or %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1198,7 +1197,7 @@
orc %3,%1,%0\;or %3,%3,%2
orc %3,%1,%0\;or %3,%3,%2
orc %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1216,7 +1215,7 @@
xor %3,%1,%0\;or %3,%3,%2
xor %3,%1,%0\;or %3,%3,%2
xor %4,%1,%0\;or %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1234,7 +1233,7 @@
and %3,%1,%0\;orc %3,%3,%2
and %3,%1,%0\;orc %3,%3,%2
and %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1252,7 +1251,7 @@
andc %3,%1,%0\;orc %3,%3,%2
andc %3,%1,%0\;orc %3,%3,%2
andc %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1270,7 +1269,7 @@
eqv %3,%1,%0\;orc %3,%3,%2
eqv %3,%1,%0\;orc %3,%3,%2
eqv %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1288,7 +1287,7 @@
nand %3,%1,%0\;orc %3,%3,%2
nand %3,%1,%0\;orc %3,%3,%2
nand %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1306,7 +1305,7 @@
nor %3,%1,%0\;orc %3,%3,%2
nor %3,%1,%0\;orc %3,%3,%2
nor %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1324,7 +1323,7 @@
or %3,%1,%0\;orc %3,%3,%2
or %3,%1,%0\;orc %3,%3,%2
or %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1342,7 +1341,7 @@
orc %3,%1,%0\;orc %3,%3,%2
orc %3,%1,%0\;orc %3,%3,%2
orc %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1360,7 +1359,7 @@
xor %3,%1,%0\;orc %3,%3,%2
xor %3,%1,%0\;orc %3,%3,%2
xor %4,%1,%0\;orc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1378,7 +1377,7 @@
and %3,%1,%0\;xor %3,%3,%2
and %3,%1,%0\;xor %3,%3,%2
and %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1396,7 +1395,7 @@
andc %3,%1,%0\;xor %3,%3,%2
andc %3,%1,%0\;xor %3,%3,%2
andc %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1414,7 +1413,7 @@
eqv %3,%1,%0\;xor %3,%3,%2
eqv %3,%1,%0\;xor %3,%3,%2
eqv %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1432,7 +1431,7 @@
nand %3,%1,%0\;xor %3,%3,%2
nand %3,%1,%0\;xor %3,%3,%2
nand %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1450,7 +1449,7 @@
nor %3,%1,%0\;xor %3,%3,%2
nor %3,%1,%0\;xor %3,%3,%2
nor %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1468,7 +1467,7 @@
or %3,%1,%0\;xor %3,%3,%2
or %3,%1,%0\;xor %3,%3,%2
or %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1486,7 +1485,7 @@
orc %3,%1,%0\;xor %3,%3,%2
orc %3,%1,%0\;xor %3,%3,%2
orc %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1504,7 +1503,7 @@
xor %3,%1,%0\;xor %3,%3,%2
xor %3,%1,%0\;xor %3,%3,%2
xor %4,%1,%0\;xor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_arithlog")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1522,7 +1521,7 @@
vand %3,%1,%0\;vand %3,%3,%2
vand %3,%1,%0\;vand %3,%3,%2
vand %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1540,7 +1539,7 @@
vandc %3,%1,%0\;vand %3,%3,%2
vandc %3,%1,%0\;vand %3,%3,%2
vandc %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1558,7 +1557,7 @@
veqv %3,%1,%0\;vand %3,%3,%2
veqv %3,%1,%0\;vand %3,%3,%2
veqv %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1576,7 +1575,7 @@
vnand %3,%1,%0\;vand %3,%3,%2
vnand %3,%1,%0\;vand %3,%3,%2
vnand %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1594,7 +1593,7 @@
vnor %3,%1,%0\;vand %3,%3,%2
vnor %3,%1,%0\;vand %3,%3,%2
vnor %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1612,7 +1611,7 @@
vor %3,%1,%0\;vand %3,%3,%2
vor %3,%1,%0\;vand %3,%3,%2
vor %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1630,7 +1629,7 @@
vorc %3,%1,%0\;vand %3,%3,%2
vorc %3,%1,%0\;vand %3,%3,%2
vorc %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1648,7 +1647,7 @@
vxor %3,%1,%0\;vand %3,%3,%2
vxor %3,%1,%0\;vand %3,%3,%2
vxor %4,%1,%0\;vand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1666,7 +1665,7 @@
vand %3,%1,%0\;vandc %3,%3,%2
vand %3,%1,%0\;vandc %3,%3,%2
vand %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1684,7 +1683,7 @@
vandc %3,%1,%0\;vandc %3,%3,%2
vandc %3,%1,%0\;vandc %3,%3,%2
vandc %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1702,7 +1701,7 @@
veqv %3,%1,%0\;vandc %3,%3,%2
veqv %3,%1,%0\;vandc %3,%3,%2
veqv %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1720,7 +1719,7 @@
vnand %3,%1,%0\;vandc %3,%3,%2
vnand %3,%1,%0\;vandc %3,%3,%2
vnand %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1738,7 +1737,7 @@
vnor %3,%1,%0\;vandc %3,%3,%2
vnor %3,%1,%0\;vandc %3,%3,%2
vnor %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1756,7 +1755,7 @@
vor %3,%1,%0\;vandc %3,%3,%2
vor %3,%1,%0\;vandc %3,%3,%2
vor %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1774,7 +1773,7 @@
vorc %3,%1,%0\;vandc %3,%3,%2
vorc %3,%1,%0\;vandc %3,%3,%2
vorc %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1792,7 +1791,7 @@
vxor %3,%1,%0\;vandc %3,%3,%2
vxor %3,%1,%0\;vandc %3,%3,%2
vxor %4,%1,%0\;vandc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1810,7 +1809,7 @@
vand %3,%1,%0\;veqv %3,%3,%2
vand %3,%1,%0\;veqv %3,%3,%2
vand %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1828,7 +1827,7 @@
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %3,%1,%0\;veqv %3,%3,%2
vandc %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1846,7 +1845,7 @@
veqv %3,%1,%0\;veqv %3,%3,%2
veqv %3,%1,%0\;veqv %3,%3,%2
veqv %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1864,7 +1863,7 @@
vnand %3,%1,%0\;veqv %3,%3,%2
vnand %3,%1,%0\;veqv %3,%3,%2
vnand %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1882,7 +1881,7 @@
vnor %3,%1,%0\;veqv %3,%3,%2
vnor %3,%1,%0\;veqv %3,%3,%2
vnor %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1900,7 +1899,7 @@
vor %3,%1,%0\;veqv %3,%3,%2
vor %3,%1,%0\;veqv %3,%3,%2
vor %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1918,7 +1917,7 @@
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %3,%1,%0\;veqv %3,%3,%2
vorc %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1936,7 +1935,7 @@
vxor %3,%1,%0\;veqv %3,%3,%2
vxor %3,%1,%0\;veqv %3,%3,%2
vxor %4,%1,%0\;veqv %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1954,7 +1953,7 @@
vand %3,%1,%0\;vnand %3,%3,%2
vand %3,%1,%0\;vnand %3,%3,%2
vand %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1972,7 +1971,7 @@
vandc %3,%1,%0\;vnand %3,%3,%2
vandc %3,%1,%0\;vnand %3,%3,%2
vandc %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -1990,7 +1989,7 @@
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %3,%1,%0\;vnand %3,%3,%2
veqv %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2008,7 +2007,7 @@
vnand %3,%1,%0\;vnand %3,%3,%2
vnand %3,%1,%0\;vnand %3,%3,%2
vnand %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2026,7 +2025,7 @@
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %3,%1,%0\;vnand %3,%3,%2
vnor %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2044,7 +2043,7 @@
vor %3,%1,%0\;vnand %3,%3,%2
vor %3,%1,%0\;vnand %3,%3,%2
vor %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2062,7 +2061,7 @@
vorc %3,%1,%0\;vnand %3,%3,%2
vorc %3,%1,%0\;vnand %3,%3,%2
vorc %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2080,7 +2079,7 @@
vxor %3,%1,%0\;vnand %3,%3,%2
vxor %3,%1,%0\;vnand %3,%3,%2
vxor %4,%1,%0\;vnand %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2098,7 +2097,7 @@
vand %3,%1,%0\;vnor %3,%3,%2
vand %3,%1,%0\;vnor %3,%3,%2
vand %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2116,7 +2115,7 @@
vandc %3,%1,%0\;vnor %3,%3,%2
vandc %3,%1,%0\;vnor %3,%3,%2
vandc %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2134,7 +2133,7 @@
veqv %3,%1,%0\;vnor %3,%3,%2
veqv %3,%1,%0\;vnor %3,%3,%2
veqv %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2152,7 +2151,7 @@
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %3,%1,%0\;vnor %3,%3,%2
vnand %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2170,7 +2169,7 @@
vnor %3,%1,%0\;vnor %3,%3,%2
vnor %3,%1,%0\;vnor %3,%3,%2
vnor %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2188,7 +2187,7 @@
vor %3,%1,%0\;vnor %3,%3,%2
vor %3,%1,%0\;vnor %3,%3,%2
vor %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2206,7 +2205,7 @@
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %3,%1,%0\;vnor %3,%3,%2
vorc %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2224,7 +2223,7 @@
vxor %3,%1,%0\;vnor %3,%3,%2
vxor %3,%1,%0\;vnor %3,%3,%2
vxor %4,%1,%0\;vnor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2242,7 +2241,7 @@
vand %3,%1,%0\;vor %3,%3,%2
vand %3,%1,%0\;vor %3,%3,%2
vand %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2260,7 +2259,7 @@
vandc %3,%1,%0\;vor %3,%3,%2
vandc %3,%1,%0\;vor %3,%3,%2
vandc %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2278,7 +2277,7 @@
veqv %3,%1,%0\;vor %3,%3,%2
veqv %3,%1,%0\;vor %3,%3,%2
veqv %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2296,7 +2295,7 @@
vnand %3,%1,%0\;vor %3,%3,%2
vnand %3,%1,%0\;vor %3,%3,%2
vnand %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2314,7 +2313,7 @@
vnor %3,%1,%0\;vor %3,%3,%2
vnor %3,%1,%0\;vor %3,%3,%2
vnor %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2332,7 +2331,7 @@
vor %3,%1,%0\;vor %3,%3,%2
vor %3,%1,%0\;vor %3,%3,%2
vor %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2350,7 +2349,7 @@
vorc %3,%1,%0\;vor %3,%3,%2
vorc %3,%1,%0\;vor %3,%3,%2
vorc %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2368,7 +2367,7 @@
vxor %3,%1,%0\;vor %3,%3,%2
vxor %3,%1,%0\;vor %3,%3,%2
vxor %4,%1,%0\;vor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2386,7 +2385,7 @@
vand %3,%1,%0\;vorc %3,%3,%2
vand %3,%1,%0\;vorc %3,%3,%2
vand %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2404,7 +2403,7 @@
vandc %3,%1,%0\;vorc %3,%3,%2
vandc %3,%1,%0\;vorc %3,%3,%2
vandc %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2422,7 +2421,7 @@
veqv %3,%1,%0\;vorc %3,%3,%2
veqv %3,%1,%0\;vorc %3,%3,%2
veqv %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2440,7 +2439,7 @@
vnand %3,%1,%0\;vorc %3,%3,%2
vnand %3,%1,%0\;vorc %3,%3,%2
vnand %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2458,7 +2457,7 @@
vnor %3,%1,%0\;vorc %3,%3,%2
vnor %3,%1,%0\;vorc %3,%3,%2
vnor %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2476,7 +2475,7 @@
vor %3,%1,%0\;vorc %3,%3,%2
vor %3,%1,%0\;vorc %3,%3,%2
vor %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2494,7 +2493,7 @@
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %3,%1,%0\;vorc %3,%3,%2
vorc %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2512,7 +2511,7 @@
vxor %3,%1,%0\;vorc %3,%3,%2
vxor %3,%1,%0\;vorc %3,%3,%2
vxor %4,%1,%0\;vorc %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2530,7 +2529,7 @@
vand %3,%1,%0\;vxor %3,%3,%2
vand %3,%1,%0\;vxor %3,%3,%2
vand %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2548,7 +2547,7 @@
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %3,%1,%0\;vxor %3,%3,%2
vandc %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2566,7 +2565,7 @@
veqv %3,%1,%0\;vxor %3,%3,%2
veqv %3,%1,%0\;vxor %3,%3,%2
veqv %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2584,7 +2583,7 @@
vnand %3,%1,%0\;vxor %3,%3,%2
vnand %3,%1,%0\;vxor %3,%3,%2
vnand %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2602,7 +2601,7 @@
vnor %3,%1,%0\;vxor %3,%3,%2
vnor %3,%1,%0\;vxor %3,%3,%2
vnor %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2620,7 +2619,7 @@
vor %3,%1,%0\;vxor %3,%3,%2
vor %3,%1,%0\;vxor %3,%3,%2
vor %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2638,7 +2637,7 @@
vorc %3,%1,%0\;vxor %3,%3,%2
vorc %3,%1,%0\;vxor %3,%3,%2
vorc %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
@@ -2656,6 +2655,6 @@
vxor %3,%1,%0\;vxor %3,%3,%2
vxor %3,%1,%0\;vxor %3,%3,%2
vxor %4,%1,%0\;vxor %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "fuse_vec")
(set_attr "cost" "6")
(set_attr "length" "8")])
diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl
index e1c45f57065..989ad5b784a 100755
--- a/gcc/config/rs6000/genfusion.pl
+++ b/gcc/config/rs6000/genfusion.pl
@@ -132,7 +132,7 @@ sub gen_ld_cmpi_p10
print " (set (match_dup 2)\n";
print " (compare:${ccmode} (match_dup 0) (match_dup 3)))]\n";
print " \"\"\n";
- print " [(set_attr \"type\" \"load\")\n";
+ print " [(set_attr \"type\" \"fuse_ldcmpi\")\n";
print " (set_attr \"cost\" \"8\")\n";
print " (set_attr \"length\" \"8\")])\n";
print "\n";
@@ -156,18 +156,20 @@ sub gen_2logical
my ($kind, $vchr, $mode, $pred, $constraint, $cr, $outer, $outer_op,
$outer_comp, $outer_inv, $outer_rtl, $inner, $inner_comp, $inner_inv,
$inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0,
- $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn);
+ $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $insn, $fuse_type);
KIND: foreach $kind ('scalar','vector') {
if ( $kind eq 'vector' ) {
$vchr = "v";
$mode = "VM";
$pred = "altivec_register_operand";
$constraint = "v";
+ $fuse_type = "fuse_vec";
} else {
$vchr = "";
$mode = "GPR";
$pred = "gpc_reg_operand";
$constraint = "r";
+ $fuse_type = "fuse_arithlog";
}
$c4 = "${constraint},${constraint},${constraint},${constraint}";
OUTER: foreach $outer ( @logicals ) {
@@ -224,7 +226,7 @@ sub gen_2logical
${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
${inner_op} %3,%1,%0\\;${outer_op} %3,%3,%2
${inner_op} %4,%1,%0\\;${outer_op} %3,%4,%2"
- [(set_attr "type" "logical")
+ [(set_attr "type" "$fuse_type")
(set_attr "cost" "6")
(set_attr "length" "8")])
EOF
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index a1904b35f7f..1d5420d6a23 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -204,7 +204,9 @@
vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,
vecfloat,vecfdiv,vecdouble,mtvsr,mfvsr,crypto,
veclogical,veccmpfx,vecexts,vecmove,
- htm,htmsimple,dfp,mma"
+ htm,htmsimple,dfp,mma,
+ fuse_arithlog,fuse_cmpisel,fuse_carry,fuse_ldcmpi,
+ fuse_ldld,fuse_stst,fuse_addisld,fuse_mtbc,fuse_vec"
(const_string "integer"))
;; What data size does this instruction work on?
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