[gcc r11-3455] testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn, uzp, zip}_half.c

[Christophe Lyon]

https://gcc.gnu.org/g:8c775bf447e190024fa08c55e38db94dd013a393

commit r11-3455-g8c775bf447e190024fa08c55e38db94dd013a393
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Sep 25 10:40:18 2020 +0000

    testsuite: [aarch64] Fix aarch64/advsimd-intrinsics/v{trn,uzp,zip}_half.c
    
    Since r11-3402 (g:65c9878641cbe0ed898aa7047b7b994e9d4a5bb1), the
    vtrn_half, vuzp_half and vzip_half started failing with
    
    vtrn_half.c:76:17: error: redeclaration of 'vector_float64x2' with no linkage
    vtrn_half.c:77:17: error: redeclaration of 'vector2_float64x2' with no linkage
    vtrn_half.c:80:17: error: redeclaration of 'vector_res_float64x2' with no linkage
    
    This is because r11-3402 now always declares float64x2 variables for
    aarch64, leading to a duplicate declaration in these testcases.
    
    The fix is simply to remove these now useless declarations.
    
    These tests are skipped on arm*, so there is no impact on that target.
    
    2020-09-25  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Remove
            declarations of vector, vector2, vector_res for float64x2 type.
            * gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise.
            * gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise.

Diff:
---
 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c | 3 ---
 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c | 3 ---
 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c | 3 ---
 3 files changed, 9 deletions(-)

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
index 63f820fbf5a..25a0f198518 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c
@@ -73,11 +73,8 @@ void exec_vtrn_half (void)
   /* Input vector can only have 64 bits.  */
   DECL_VARIABLE_ALL_VARIANTS(vector);
   DECL_VARIABLE_ALL_VARIANTS(vector2);
-  DECL_VARIABLE(vector, float, 64, 2);
-  DECL_VARIABLE(vector2, float, 64, 2);
 
   DECL_VARIABLE_ALL_VARIANTS(vector_res);
-  DECL_VARIABLE(vector_res, float, 64, 2);
 
   clean_results ();
   /* We don't have vtrn1_T64x1, so set expected to the clean value.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
index 8706f248591..2e6b666b71d 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c
@@ -70,11 +70,8 @@ void exec_vuzp_half (void)
   /* Input vector can only have 64 bits.  */
   DECL_VARIABLE_ALL_VARIANTS(vector);
   DECL_VARIABLE_ALL_VARIANTS(vector2);
-  DECL_VARIABLE(vector, float, 64, 2);
-  DECL_VARIABLE(vector2, float, 64, 2);
 
   DECL_VARIABLE_ALL_VARIANTS(vector_res);
-  DECL_VARIABLE(vector_res, float, 64, 2);
 
   clean_results ();
   /* We don't have vuzp1_T64x1, so set expected to the clean value.  */
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
index 619d6b2e6ed..ef42451c82e 100644
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vzip_half.c
@@ -73,11 +73,8 @@ void exec_vzip_half (void)
   /* Input vector can only have 64 bits.  */
   DECL_VARIABLE_ALL_VARIANTS(vector);
   DECL_VARIABLE_ALL_VARIANTS(vector2);
-  DECL_VARIABLE(vector, float, 64, 2);
-  DECL_VARIABLE(vector2, float, 64, 2);
 
   DECL_VARIABLE_ALL_VARIANTS(vector_res);
-  DECL_VARIABLE(vector_res, float, 64, 2);
 
   clean_results ();
   /* We don't have vzip1_T64x1, so set expected to the clean value.  */