[gcc(refs/users/meissner/heads/work018)] Undo patch.
Michael Meissner
meissner@gcc.gnu.org
Thu Sep 17 06:36:17 GMT 2020
https://gcc.gnu.org/g:21944404fa98973057379753c41a7e4ddec55d31
commit 21944404fa98973057379753c41a7e4ddec55d31
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Sep 17 02:35:26 2020 -0400
Undo patch.
gcc/
2020-09-17 Michael Meissner <meissner@linux.ibm.com>
Undo:
* config.gcc (powerpc*-*-*): Add pcrel-opt.o.
(rs6000*-*-*): Add pcrel-opt.o.
* config/rs6000/pcrel-opt.c: New file.
* config/rs6000/pcrel-opt.md: New file.
* config/rs6000/predicates.md (d_form_memory): New predicate.
* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
-mpcrel-opt.
(POWERPC_MASKS): Add -mpcrel-opt.
* config/rs6000/rs6000-passes.def: Add comment for existing power8
swaps pass. Add PCREL_OPT pass.
* config/rs6000/rs6000-protos.h (reg_to_non_prefixed): New
declaration.
(offsettable_non_prefixed_memory): New declaration.
(output_pcrel_opt_reloc): New declaration.
(make_pass_pcrel_opt): New declaration.
* config/rs6000/rs6000.c (reg_to_non_prefixed): Make function
globally visible.
(rs6000_option_override_internal): Add support for -mpcrel-opt.
(rs6000_delegitimize_address): Add support for the PCREL_OPT
addresses.
(rs6000_opt_masks): Add -mpcrel-opt.
(offsettable_non_prefixed_memory): New helper function.
(rs6000_asm_output_opcode): Reset prefixed flag after first use.
(output_pcrel_opt_reloc): New function.
* config/rs6000/rs6000.md (loads_extern_addr): New insn
attribute.
(pcrel_extern_addr): Set loads_extern_addr attribute.
(toplevel): Include pcrel-opt.md.
* config/rs6000/rs6000.opt (-mpcrel-opt): New option.
* config/rs6000/t-rs6000 (pcrel-opt.o): Add build rules.
(MD_INCLUDES): Add pcrel-opt.md
gcc/
2020-09-17 Michael Meissner <meissner@linux.ibm.com>
Undo:
* config/rs6000/pcrel-opt.c (pcrel_opt_store): New function.
(pcrel_opt_address): Add PCREL_OPT support for stores.
(pcrel_opt_pass): Print PCREL_OPT store statistics.
* config/rs6000/pcrel-opt.md (UNSPEC_PCREL_OPT_ST_ADDR): New
unspec.
(UNSPEC_PCREL_OPT_ST_RELOC): New unspec.
(pcrel_opt_st_addr<mode>): New insns for PCREL_OPT store support.
(pcrel_opt_st<mode>, QHSI iterator): New insns for PCREL_OPT store
support.
(pcrel_opt_stdi): New insn for PCREL_OPT store support.
(pcrel_opt_stsf): New insn for PCREL_OPT store support.
(pcrel_opt_stdf): New insns for PCREL_OPT store support.
(pcrel_opt_st<mode>, PO_VECT iterator): New insns for PCREL_OPT
store support.
* config/rs6000/rs6000.c (rs6000_delegitimize_address): Add
support for PCREL_OPT store.
Diff:
---
gcc/config.gcc | 6 +-
gcc/config/rs6000/predicates.md | 23 -------
gcc/config/rs6000/rs6000-cpus.def | 2 -
gcc/config/rs6000/rs6000-passes.def | 8 ---
gcc/config/rs6000/rs6000-protos.h | 4 --
gcc/config/rs6000/rs6000.c | 116 ++----------------------------------
gcc/config/rs6000/rs6000.md | 8 +--
gcc/config/rs6000/rs6000.opt | 4 --
gcc/config/rs6000/t-rs6000 | 7 +--
9 files changed, 9 insertions(+), 169 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 707cd54c822..845f10e48be 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -505,7 +505,7 @@ or1k*-*-*)
;;
powerpc*-*-*)
cpu_type=rs6000
- extra_objs="rs6000-string.o rs6000-p8swap.o rs6000-logue.o rs6000-call.o pcrel-opt.o"
+ extra_objs="rs6000-string.o rs6000-p8swap.o rs6000-logue.o rs6000-call.o"
extra_headers="ppc-asm.h altivec.h htmintrin.h htmxlintrin.h"
extra_headers="${extra_headers} bmi2intrin.h bmiintrin.h"
extra_headers="${extra_headers} xmmintrin.h mm_malloc.h emmintrin.h"
@@ -520,7 +520,6 @@ powerpc*-*-*)
esac
extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
target_gtfiles="$target_gtfiles \$(srcdir)/config/rs6000/rs6000-logue.c \$(srcdir)/config/rs6000/rs6000-call.c"
- target_gtfiles="$target_gtfiles \$(srcdir)/config/rs6000/pcrel-opt.c"
;;
pru-*-*)
cpu_type=pru
@@ -532,9 +531,8 @@ riscv*)
;;
rs6000*-*-*)
extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
- extra_objs="rs6000-string.o rs6000-p8swap.o rs6000-logue.o rs6000-call.o pcrel-opt.o"
+ extra_objs="rs6000-string.o rs6000-p8swap.o rs6000-logue.o rs6000-call.o"
target_gtfiles="$target_gtfiles \$(srcdir)/config/rs6000/rs6000-logue.c \$(srcdir)/config/rs6000/rs6000-call.c"
- target_gtfiles="$target_gtfiles \$(srcdir)/config/rs6000/pcrel-opt.c"
;;
sparc*-*-*)
cpu_type=sparc
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 9610587e1c1..4c2fe7fa312 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1876,26 +1876,3 @@
{
return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT);
})
-
-;; Return true if the operand is a valid memory operand with an offsettable
-;; address that could be merged with the load of a PC-relative external address
-;; with the PCREL_OPT optimization. We don't check here whether or not the
-;; offset needs to be used in a DS-FORM (bottom 2 bits 0) or DQ-FORM (bottom 4
-;; bits 0) instruction.
-(define_predicate "d_form_memory"
- (match_code "mem")
-{
- if (!memory_operand (op, mode))
- return false;
-
- rtx addr = XEXP (op, 0);
-
- if (REG_P (addr) || SUBREG_P (addr))
- return true;
-
- if (GET_CODE (addr) != PLUS)
- return false;
-
- return (base_reg_operand (XEXP (addr, 0), Pmode)
- && satisfies_constraint_I (XEXP (addr, 1)));
-})
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index d3f72d77a6e..8d2c1ffd6cf 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -78,7 +78,6 @@
/* Flags that need to be turned off if -mno-power10. */
#define OTHER_POWER10_MASKS (OPTION_MASK_MMA \
| OPTION_MASK_PCREL \
- | OPTION_MASK_PCREL_OPT \
| OPTION_MASK_PREFIXED)
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
@@ -143,7 +142,6 @@
| OPTION_MASK_P9_MISC \
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_PCREL \
- | OPTION_MASK_PCREL_OPT \
| OPTION_MASK_POPCNTB \
| OPTION_MASK_POPCNTD \
| OPTION_MASK_POWERPC64 \
diff --git a/gcc/config/rs6000/rs6000-passes.def b/gcc/config/rs6000/rs6000-passes.def
index b62244b8df2..5164c526e34 100644
--- a/gcc/config/rs6000/rs6000-passes.def
+++ b/gcc/config/rs6000/rs6000-passes.def
@@ -24,12 +24,4 @@ along with GCC; see the file COPYING3. If not see
REPLACE_PASS (PASS, INSTANCE, TGT_PASS)
*/
- /* Pass to add the appropriate vector swaps on power8 little endian systems.
- The power8 does not have instructions that automaticaly do the byte swaps
- for loads and stores. */
INSERT_PASS_BEFORE (pass_cse, 1, pass_analyze_swaps);
-
- /* Pass to do the PCREL_OPT optimization that combines the load of an
- external symbol's address along with a single load or store using that
- address as a base register. */
- INSERT_PASS_BEFORE (pass_sched2, 1, pass_pcrel_opt);
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 75c659971ea..25fa5dd57cd 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -190,13 +190,10 @@ enum non_prefixed_form {
extern enum insn_form address_to_insn_form (rtx, machine_mode,
enum non_prefixed_form);
-extern enum non_prefixed_form reg_to_non_prefixed (rtx, machine_mode);
-extern bool offsettable_non_prefixed_memory (rtx, machine_mode, rtx);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
-extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
extern int rs6000_adjust_insn_length (rtx_insn *, int);
@@ -309,7 +306,6 @@ namespace gcc { class context; }
class rtl_opt_pass;
extern rtl_opt_pass *make_pass_analyze_swaps (gcc::context *);
-extern rtl_opt_pass *make_pass_pcrel_opt (gcc::context *);
extern bool rs6000_sum_of_two_registers_p (const_rtx expr);
extern bool rs6000_quadword_masked_address_p (const_rtx exp);
extern rtx rs6000_gen_lvx (enum machine_mode, rtx, rtx);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index b589f4566c2..92b080a96df 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1175,6 +1175,7 @@ static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
machine_mode,
secondary_reload_info *,
bool);
+static enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
/* Hash table stuff for keeping track of TOC entries. */
@@ -4324,14 +4325,6 @@ rs6000_option_override_internal (bool global_init_p)
rs6000_isa_flags &= ~OPTION_MASK_MMA;
}
- if (!TARGET_PCREL && TARGET_PCREL_OPT)
- {
- if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL_OPT) != 0)
- error ("%qs requires %qs", "-mpcrel-opt", "-mpcrel");
-
- rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
- }
-
if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
@@ -8531,57 +8524,8 @@ rs6000_delegitimize_address (rtx orig_x)
{
rtx x, y, offset;
- /* UNSPEC_FUSION_GPR is created by the peephole2 for power8 fusion. It
- encodes loading up the high part of the address of a TOC reference along
- with a load of a GPR using the same base register used for the load. We
- return the original SYMBOL_REF.
-
- (set (reg:INT1 <reg>
- (unspec:INT1 [<combined-address>] UNSPEC_FUSION_GPR)))
-
- UNSPEC_PCREL_OPT_LD_ADDR is used by the power10 PCREL_OPT pass. These
- UNSPECs include the external SYMBOL_REF along with the value being loaded.
- We return the original SYMBOL_REF.
-
- (parallel [(set (reg:DI <base-reg>)
- (unspec:DI [(symbol_ref <symbol>)
- (const_int <marker>)]
- UNSPEC_PCREL_OPT_LD_ADDR))
- (set (reg:DI <load-reg>)
- (unspec:DI [(const_int 0)]
- UNSPEC_PCREL_OPT_LD_ADDR))])
-
- UNSPEC_PCREL_OPT_LD_ADDR_SAME_REG is an alternative that is used if the
- GPR being loaded is the same as the GPR used to hold the external address.
-
- (set (reg:DI <base-reg>)
- (unspec:DI [(symbol_ref <symbol>)
- (const_int <marker>)]
- UNSPEC_PCREL_OPT_LD_ADDR_SAME_REG))
-
- UNSPEC_PCREL_OPT_ST_ADDR is used by the power10 PCREL_OPT pass. This
- UNSPEC include the external SYMBOL_REF along with the value being loaded.
- We return the original SYMBOL_REF.
-
- (parallel [(set (reg:DI <base-reg>)
- (unspec:DI [(symbol_ref <symbol>)
- (const_int <marker>)]
- UNSPEC_PCREL_OPT_ST_ADDR))
- (use (reg <store-reg>))]) */
-
- if (GET_CODE (orig_x) == UNSPEC)
- switch (XINT (orig_x, 1))
- {
- case UNSPEC_FUSION_GPR:
- case UNSPEC_PCREL_OPT_LD_ADDR:
- case UNSPEC_PCREL_OPT_LD_ADDR_SAME_REG:
- case UNSPEC_PCREL_OPT_ST_ADDR:
- orig_x = XVECEXP (orig_x, 0, 0);
- break;
-
- default:
- break;
- }
+ if (GET_CODE (orig_x) == UNSPEC && XINT (orig_x, 1) == UNSPEC_FUSION_GPR)
+ orig_x = XVECEXP (orig_x, 0, 0);
orig_x = delegitimize_mem_from_attrs (orig_x);
@@ -23348,7 +23292,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "mulhw", OPTION_MASK_MULHW, false, true },
{ "multiple", OPTION_MASK_MULTIPLE, false, true },
{ "pcrel", OPTION_MASK_PCREL, false, true },
- { "pcrel-opt", OPTION_MASK_PCREL_OPT, false, true },
{ "popcntb", OPTION_MASK_POPCNTB, false, true },
{ "popcntd", OPTION_MASK_POPCNTD, false, true },
{ "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
@@ -25448,32 +25391,6 @@ address_to_insn_form (rtx addr,
return INSN_FORM_BAD;
}
-/* Return true if an REG with a given MODE is loaded from or stored into a MEM
- location uses a non-prefixed offsettable address. This is used to validate
- the load or store with the PCREL_OPT optimization to make sure it is an
- instruction that can be optimized.
-
- We need to specify the MODE separately from the REG to allow for loads that
- include zero/sign/float extension. */
-
-bool
-offsettable_non_prefixed_memory (rtx reg, machine_mode mode, rtx mem)
-{
- /* If the instruction is indexed only like LFIWAX/LXSIWAX, it is not
- offsettable. */
- enum non_prefixed_form non_prefixed = reg_to_non_prefixed (reg, mode);
- if (non_prefixed == NON_PREFIXED_X)
- return false;
-
- /* Check if this is a non-prefixed offsettable instruction. */
- rtx addr = XEXP (mem, 0);
- enum insn_form iform = address_to_insn_form (addr, mode, non_prefixed);
- return (iform == INSN_FORM_BASE_REG
- || iform == INSN_FORM_D
- || iform == INSN_FORM_DS
- || iform == INSN_FORM_DQ);
-}
-
/* Helper function to see if we're potentially looking at lfs/stfs.
- PARALLEL containing a SET and a CLOBBER
- stfs:
@@ -25532,7 +25449,7 @@ is_lfs_stfs_insn (rtx_insn *insn)
/* Helper function to take a REG and a MODE and turn it into the non-prefixed
instruction format (D/DS/DQ) used for offset memory. */
-enum non_prefixed_form
+static enum non_prefixed_form
reg_to_non_prefixed (rtx reg, machine_mode mode)
{
/* If it isn't a register, use the defaults. */
@@ -25755,34 +25672,11 @@ void
rs6000_asm_output_opcode (FILE *stream)
{
if (next_insn_prefixed_p)
- {
- fprintf (stream, "p");
-
- /* Reset flag in case there are separate insn lines in the sequence, so
- the 'p' is only emited for the first line. This shows up when we are
- doing the PCREL_OPT optimization, in that the label created with %r<n>
- would have a leading 'p' printed. */
- next_insn_prefixed_p = false;
- }
+ fprintf (stream, "p");
return;
}
-/* Emit the relocation to tie the next instruction to a previous instruction
- that loads up an external address. This is used to do the PCREL_OPT
- optimization. Note, the label is generated after the PLD of the got
- pc-relative address to allow for the assembler to insert NOPs before the PLD
- instruction. The operand is a constant integer that is the label
- number. */
-
-void
-output_pcrel_opt_reloc (rtx label_num)
-{
- rtx operands[1] = { label_num };
- output_asm_insn (".reloc .Lpcrel%0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel%0-8)",
- operands);
-}
-
/* Adjust the length of an INSN. LENGTH is the currently-computed length and
should be adjusted to reflect any required changes. This macro is used when
there is some systematic length adjustment required that would be difficult
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index dd9a63c395e..1aebaa7fade 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -292,10 +292,6 @@
(const_string "no")))
-;; Whether an insn loads an external address for the PCREL_OPT optimizaton.
-(define_attr "loads_extern_addr" "no,yes"
- (const_string "no"))
-
;; Return the number of real hardware instructions in a combined insn. If it
;; is 0, just use the length / 4.
(define_attr "num_insns" "" (const_int 0))
@@ -10299,8 +10295,7 @@
"TARGET_PCREL"
"ld %0,%a1"
[(set_attr "prefixed" "yes")
- (set_attr "type" "load")
- (set_attr "loads_extern_addr" "yes")])
+ (set_attr "type" "load")])
;; TOC register handling.
@@ -14974,4 +14969,3 @@
(include "dfp.md")
(include "crypto.md")
(include "htm.md")
-(include "pcrel-opt.md")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index d1719bfd2a0..b2a70e88ca8 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -586,10 +586,6 @@ mpcrel
Target Report Mask(PCREL) Var(rs6000_isa_flags)
Generate (do not generate) pc-relative memory addressing.
-mpcrel-opt
-Target Undocumented Mask(PCREL_OPT) Var(rs6000_isa_flags)
-Generate (do not generate) pc-relative memory optimizations for externals.
-
mmma
Target Report Mask(MMA) Var(rs6000_isa_flags)
Generate (do not generate) MMA instructions.
diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000
index a617276484e..1ddb5729cb2 100644
--- a/gcc/config/rs6000/t-rs6000
+++ b/gcc/config/rs6000/t-rs6000
@@ -23,10 +23,6 @@ TM_H += $(srcdir)/config/rs6000/rs6000-cpus.def
TM_H += $(srcdir)/config/rs6000/rs6000-modes.h
PASSES_EXTRA += $(srcdir)/config/rs6000/rs6000-passes.def
-pcrel-opt.o: $(srcdir)/config/rs6000/pcrel-opt.c
- $(COMPILE) $<
- $(POSTCOMPILE)
-
rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c
$(COMPILE) $<
$(POSTCOMPILE)
@@ -90,5 +86,4 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \
$(srcdir)/config/rs6000/mma.md \
$(srcdir)/config/rs6000/crypto.md \
$(srcdir)/config/rs6000/htm.md \
- $(srcdir)/config/rs6000/dfp.md \
- $(srcdir)/config/rs6000/pcrel-opt.md
+ $(srcdir)/config/rs6000/dfp.md
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