[gcc(refs/users/wschmidt/heads/builtins3)] rs6000: More built-in definitions.
William Schmidt
wschmidt@gcc.gnu.org
Thu Oct 29 19:52:32 GMT 2020
https://gcc.gnu.org/g:dd90710bc5588f159adc576de70ad321fcc9c8e9
commit dd90710bc5588f159adc576de70ad321fcc9c8e9
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Wed Aug 12 11:50:05 2020 -0500
rs6000: More built-in definitions.
2020-08-12 Bill Schmidt <wschmidt@linux.ibm.com>
* rs6000-builtin-new.def: Add some built-in definitions that were
added since the beginning of this project.
* rs6000-gen-builtins.c (header commentary): Adjust.
(bif_stanza): Add BSTZ_P10_64.
(stanza_map): Likewise.
(enable_string): Likewise.
(attrinfo): Add isquad and ispair.
(parse_bif_attrs): Handle isquad and ispair.
(write_decls): Handle ENB_P10_64, bif_quad_bit, and bif_pair_bit.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 176 ++++++++++++++++++++++++++++++-
gcc/config/rs6000/rs6000-gen-builtins.c | 35 ++++--
2 files changed, 204 insertions(+), 7 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index b6a1830c093..8586589c52b 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -2396,6 +2396,9 @@
; Power9 vector builtins.
[power9-vector]
+ const vus __builtin_altivec_convert_4f32_8f16 (vf, vf);
+ CONVERT_4F32_8F16 convert_4f32_8f16 {}
+
const vus __builtin_altivec_convert_4f32_8i16 (vf, vf);
CONVERT_4F32_8I16 convert_4f32_8i16 {}
@@ -2558,6 +2561,9 @@
const unsigned int __builtin_altivec_vextuwrx (unsigned int, vui);
VEXTUWRX vextuwrx {}
+ const vsq __builtin_altivec_vmsumudm (vsll, vsll, vsq);
+ VMSUMUDM altivec_vmsumudm {}
+
const vsll __builtin_altivec_vprtybd (vsll);
VPRTYBD parityv2di2 {}
@@ -2567,7 +2573,7 @@
const vsi __builtin_altivec_vprtybw (vsi);
VPRTYBW parityv4si2 {}
- const vull __builtiin_altivec_vrldmi (vull, vull, vull);
+ const vull __builtin_altivec_vrldmi (vull, vull, vull);
VRLDMI altivec_vrldmi {}
const vull __builtin_altivec_vrldnm (vull, vull);
@@ -2960,6 +2966,174 @@
TTEST ttest {htm,htmcr}
+[power10]
+ const unsigned long long __builtin_altivec_cntmbb (vuc, const int<1>);
+ VCNTMBB vec_cntmb_v16qi {}
+
+ const unsigned long long __builtin_altivec_cntmbd (vull, const int<1>);
+ VCNTMBD vec_cntmb_v2di {}
+
+ const unsigned long long __builtin_altivec_cntmbh (vus, const int<1>);
+ VCNTMBH vec_cntmb_v8hi {}
+
+ const unsigned long long __builtin_altivec_cntmbw (vui, const int<1>);
+ VCNTMBW vec_cntmb_v4si {}
+
+ const vuc __builtin_altivec_mtvsrbm (unsigned long long);
+ MTVSRBM vec_mtvsr_v16qi {}
+
+ const vull __builtin_altivec_mtvsrdm (unsigned long long);
+ MTVSRDM vec_mtvsr_v2di {}
+
+ const vus __builtin_altivec_mtvsrhm (unsigned long long);
+ MTVSRHM vec_mtvsr_v8hi {}
+
+ const vuq __builtin_altivec_mtvsrqm (unsigned long long);
+ MTVSRQM vec_mtvsr_v1ti {}
+
+ const vui __builtin_altivec_mtvsrwm (unsigned long long);
+ MTVSRWM vec_mtvsr_v4si {}
+
+ const vuc __builtin_altivec_vcfuged (vuc, vuc);
+ VCFUGED vcfuged {}
+
+ const vsc __builtin_altivec_vclrlb (vsc, unsigned int);
+ VCLRLB vclrlb {}
+
+ const vsc __builtin_altivec_vclrrb (vsc, unsigned int);
+ VCLRRB vclrrb {}
+
+ const vuc __builtin_altivec_vclzdm (vuc, vuc);
+ VCLZDM vclzdm {}
+
+ const vuc __builtin_altivec_vctzdm (vuc, vuc);
+ VCTZDM vctzdm {}
+
+ const vuc __builtin_altivec_vexpandmb (vuc);
+ VEXPANDMB vec_expand_v16qi {}
+
+ const vull __builtin_altivec_vexpandmd (vull);
+ VEXPANDMD vec_expand_v2di {}
+
+ const vus __builtin_altivec_vexpandmh (vus);
+ VEXPANDMH vec_expand_v8hi {}
+
+ const vuq __builtin_altivec_vexpandmq (vuq);
+ VEXPANDMQ vec_expand_v1ti {}
+
+ const vui __builtin_altivec_vexpandmw (vui);
+ VEXPANDMW vec_expand_v4si {}
+
+ const vull __builtin_altivec_vextddvhx (vull, vull, unsigned char);
+ VEXTRACTDR vextractrv2di {}
+
+ const vull __builtin_altivec_vextddvlx (vull, vull, unsigned char);
+ VEXTRACTDL vextractlv2di {}
+
+ const vull __builtin_altivec_vextdubvhx (vuc, vuc, unsigned char);
+ VEXTRACTBR vextractrv16qi {}
+
+ const vull __builtin_altivec_vextdubvlx (vuc, vuc, unsigned char);
+ VEXTRACTBL vextractlv16qi {}
+
+ const vull __builtin_altivec_vextduhvhx (vus, vus, unsigned char);
+ VEXTRACTHR vextractrv8hi {}
+
+ const vull __builtin_altivec_vextduhvlx (vus, vus, unsigned char);
+ VEXTRACTHL vextractlv8hi {}
+
+ const vull __builtin_altivec_vextduwvrx (vui, vui, unsigned char);
+ VEXTRACTWR vextractrv4si {}
+
+ const vull __builtin_altivec_vextduwvlx (vui, vui, unsigned char);
+ VEXTRACTWL vextractlv4si {}
+
+ const unsigned int __builtin_altivec_vextractmb (vuc);
+ VEXTRACTMB vec_extract_v16qi {}
+
+ const unsigned int __builtin_altivec_vextractmd (vull);
+ VEXTRACTMD vec_extract_v2di {}
+
+ const unsigned int __builtin_altivec_vextractmh (vus);
+ VEXTRACTMH vec_extract_v8hi {}
+
+ const unsigned int __builtin_altivec_vextractmq (vuq);
+ VEXTRACTMQ vec_extract_v1ti {}
+
+ const unsigned int __builtin_altivec_vextractmw (vui);
+ VEXTRACTMW vec_extract_v4si {}
+
+ const unsigned long long __builtin_altivec_vgnb (vuq, const int <2,7>);
+ VGNB vgnb {}
+
+ const vuc __builtin_altivec_vpdepd (vuc, vuc);
+ VPDEPD vpdepd {}
+
+ const vuc __builtin_altivec_vpextd (vuc, vuc);
+ VPEXTD vpextd {}
+
+ const vuc __builtin_altivec_vstribl (vuc);
+ VSTRIBL vstril_v16qi {}
+
+ const signed int __builtin_altivec_vstribl_p (vuc);
+ VSTRIBL_P vstril_p_v16qi {}
+
+ const vuc __builtin_altivec_vstribr (vuc);
+ VSTRIBR vstrir_v16qi {}
+
+ const signed int __builtin_altivec_vstribr_p (vuc);
+ VSTRIBR_P vstrir_p_v16qi {}
+
+ const vus __builtin_altivec_vstrihl (vus);
+ VSTRIHL vstril_v8hi {}
+
+ const signed int __builtin_altivec_vstrihl_p (vus);
+ VSTRIHL_P vstril_p_v8hi {}
+
+ const vus __builtin_altivec_vstrihr (vus);
+ VSTRIHR vstrir_v8hi {}
+
+ const signed int __builtin_altivec_vstrihr_p (vus);
+ VSTRIHR_P vstrir_p_v8hi {}
+
+ const vop __builtin_vsx_xxeval (vop, vop, vop, const int <8>);
+ XXEVAL xxeval {}
+
+ const vuc __builtin_vsx_xxgenpcvm_v16qi (vuc, const int <2>);
+ XXGENPCVM_V16QI xxgenpcvm_v16qi {}
+
+ const vull __builtin_vsx_xxgenpcvm_v2di (vull, const int <2>);
+ XXGENPCVM_V2DI xxgenpcvm_v2di {}
+
+ const vui __builtin_vsx_xxgenpcvm_v4si (vui, const int <2>);
+ XXGENPCVM_V4SI xxgenpcvm_v4si {}
+
+ const vus __builtin_vsx_xxgenpcvm_v8hi (vus, const int <2>);
+ XXGENPCVM_V8HI xxgenpcvm_v8hi {}
+
+ const vop __builtin_vsx_xvcvbf16sp (vop);
+ XVCVBF16SP vsx_xvcvbf16sp {}
+
+ const vop __builtin_vsx_xvcvspbf16 (vop);
+ XVCVSPBF16 vsx_xvcvspbf16 {}
+
+
+[power10-64]
+ const unsigned long long __builtin_cfuged (unsigned long long, unsigned long long);
+ CFUGED cfuged {}
+
+ const unsigned long long __builtin_cntlzdm (unsigned long long, unsigned long long);
+ CNTLZDM cntlzdm {}
+
+ const unsigned long long __builtin_cnttzdm (unsigned long long, unsigned long long);
+ CNTTZDM cnttzdm {}
+
+ const unsigned long long __builtin_pdepd (unsigned long long, unsigned long long);
+ PDEPD pdepd {}
+
+ const unsigned long long __builtin_pextd (unsigned long long, unsigned long long);
+ PEXTD pextd {}
+
; #### We don't yet have the Darwin CfString builtin supported, but
; that has its own special handling so it should go in there, I guess.
;
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index 1d83215b32a..e77877da9c4 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -82,6 +82,8 @@ along with GCC; see the file COPYING3. If not see
htmspr HTM function using an SPR
htmcr HTM function using a CR
mma Needs special handling for MMA instructions
+ quad MMA instruction using a register quad as an input operand
+ pair MMA instruction using a register pair as an input operand
no32bit Not valid for TARGET_32BIT
cpu This is a "cpu_is" or "cpu_supports" builtin
ldstmask Altivec mask for load or store
@@ -194,6 +196,7 @@ enum bif_stanza {
BSTZ_CRYPTO,
BSTZ_HTM,
BSTZ_P10,
+ BSTZ_P10_64,
BSTZ_MMA,
NUMBIFSTANZAS
};
@@ -225,6 +228,7 @@ static stanza_entry stanza_map[NUMBIFSTANZAS] =
{ "crypto", BSTZ_CRYPTO },
{ "htm", BSTZ_HTM },
{ "power10", BSTZ_P10 },
+ { "power10-64", BSTZ_P10_64 },
{ "mma", BSTZ_MMA }
};
@@ -247,6 +251,7 @@ static const char *enable_string[NUMBIFSTANZAS] =
"ENB_CRYPTO",
"ENB_HTM",
"ENB_P10",
+ "ENB_P10_64",
"ENB_MMA"
};
@@ -328,6 +333,8 @@ struct attrinfo {
char ishtmspr;
char ishtmcr;
char ismma;
+ char isquad;
+ char ispair;
char isno32bit;
char iscpu;
char isldstmask;
@@ -1260,6 +1267,10 @@ parse_bif_attrs (attrinfo *attrptr)
attrptr->ishtmcr = 1;
else if (!strcmp (attrname, "mma"))
attrptr->ismma = 1;
+ else if (!strcmp (attrname, "quad"))
+ attrptr->isquad = 1;
+ else if (!strcmp (attrname, "pair"))
+ attrptr->ispair = 1;
else if (!strcmp (attrname, "no32bit"))
attrptr->isno32bit = 1;
else if (!strcmp (attrname, "cpu"))
@@ -1297,12 +1308,13 @@ parse_bif_attrs (attrinfo *attrptr)
#ifdef DEBUG
(*diag) ("attribute set: init = %d, set = %d, extract = %d, \
nosoft = %d, ldvec = %d, stvec = %d, reve = %d, pred = %d, htm = %d, \
-htmspr = %d, htmcr = %d, mma = %d, no32bit = %d, cpu = %d, ldstmask = %d.\n",
+htmspr = %d, htmcr = %d, mma = %d, quad = %d, pair = %d, no32bit = %d, \
+cpu = %d, ldstmask = %d.\n",
attrptr->isinit, attrptr->isset, attrptr->isextract,
attrptr->isnosoft, attrptr->isldvec, attrptr->isstvec,
attrptr->isreve, attrptr->ispred, attrptr->ishtm, attrptr->ishtmspr,
- attrptr->ishtmcr, attrptr->ismma, attrptr->isno32bit,
- attrptr->iscpu, attrptr->isldstmask);
+ attrptr->ishtmcr, attrptr->ismma, attrptr->isquad, attriptr->ispair,
+ attrptr->isno32bit, attrptr->iscpu, attrptr->isldstmask);
#endif
return PC_OK;
@@ -1987,6 +1999,7 @@ write_decls ()
fprintf (header_file, " ENB_CRYPTO,\n");
fprintf (header_file, " ENB_HTM,\n");
fprintf (header_file, " ENB_P10,\n");
+ fprintf (header_file, " ENB_P10_64,\n");
fprintf (header_file, " ENB_MMA\n");
fprintf (header_file, "};\n\n");
@@ -2016,9 +2029,11 @@ write_decls ()
fprintf (header_file, "#define bif_htmspr_bit\t\t(0x00000200)\n");
fprintf (header_file, "#define bif_htmcr_bit\t\t(0x00000400)\n");
fprintf (header_file, "#define bif_mma_bit\t\t(0x00000800)\n");
- fprintf (header_file, "#define bif_no32bit_bit\t\t(0x00001000)\n");
- fprintf (header_file, "#define bif_cpu_bit\t\t(0x00002000)\n");
- fprintf (header_file, "#define bif_ldstmask_bit\t(0x00004000)\n");
+ fprintf (header_file, "#define bif_quad_bit\t\t(0x00001000)\n");
+ fprintf (header_file, "#define bif_pair_bit\t\t(0x00002000)\n");
+ fprintf (header_file, "#define bif_no32bit_bit\t\t(0x00004000)\n");
+ fprintf (header_file, "#define bif_cpu_bit\t\t(0x00008000)\n");
+ fprintf (header_file, "#define bif_ldstmask_bit\t(0x00010000)\n");
fprintf (header_file, "\n");
fprintf (header_file,
"#define bif_is_init(x)\t\t((x).bifattrs & bif_init_bit)\n");
@@ -2044,6 +2059,10 @@ write_decls ()
"#define bif_is_htmcr(x)\t\t((x).bifattrs & bif_htmcr_bit)\n");
fprintf (header_file,
"#define bif_is_mma(x)\t\t((x).bifattrs & bif_mma_bit)\n");
+ fprintf (header_file,
+ "#define bif_is_quad(x)\t\t((x).bifattrs & bif_quad_bit)\n");
+ fprintf (header_file,
+ "#define bif_is_pair(x)\t\t((x).bifattrs & bif_pair_bit)\n");
fprintf (header_file,
"#define bif_is_no32bit(x)\t((x).bifattrs & bif_no32bit_bit)\n");
fprintf (header_file,
@@ -2262,6 +2281,10 @@ write_init_bif_table ()
fprintf (init_file, " | bif_htmcr_bit");
if (bifs[i].attrs.ismma)
fprintf (init_file, " | bif_mma_bit");
+ if (bifs[i].attrs.isquad)
+ fprintf (init_file, " | bif_quad_bit");
+ if (bifs[i].attrs.ispair)
+ fprintf (init_file, " | bif_pair_bit");
if (bifs[i].attrs.isno32bit)
fprintf (init_file, " | bif_no32bit_bit");
if (bifs[i].attrs.iscpu)
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