[gcc(refs/users/meissner/heads/work023)] Power10: Add int128 divide, modulus.
Michael Meissner
meissner@gcc.gnu.org
Wed Oct 28 03:47:57 GMT 2020
https://gcc.gnu.org/g:4a3e99756140d1db97681eed52d8108931b817a6
commit 4a3e99756140d1db97681eed52d8108931b817a6
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Oct 27 23:47:31 2020 -0400
Power10: Add int128 divide, modulus.
gcc/
2020-10-27 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.c (divti3): New insn.
(udivti3): New insn.
(modti3): New insn.
(umodti3): New insn.
Diff:
---
gcc/config/rs6000/rs6000.md | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3822affa2ec..0edfffcf255 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3416,6 +3416,38 @@
(minus:GPR (match_dup 1)
(match_dup 3)))])
+(define_insn "divti3"
+ [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
+ (div:TI (match_operand:TI 1 "gpc_reg_operand" "v")
+ (match_operand:TI 2 "gpc_reg_operand" "v")))]
+ "TARGET_POWER10"
+ "vdivsq %0,%1,%2"
+ [(set_attr "type" "vecdiv")])
+
+(define_insn "udivti3"
+ [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
+ (udiv:TI (match_operand:TI 1 "gpc_reg_operand" "v")
+ (match_operand:TI 2 "gpc_reg_operand" "v")))]
+ "TARGET_POWER10"
+ "vdivuq %0,%1,%2"
+ [(set_attr "type" "vecdiv")])
+
+(define_insn "modti3"
+ [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
+ (mod:TI (match_operand:TI 1 "gpc_reg_operand" "v")
+ (match_operand:TI 2 "gpc_reg_operand" "v")))]
+ "TARGET_POWER10"
+ "vmodsq %0,%1,%2"
+ [(set_attr "type" "vecdiv")])
+
+(define_insn "umodti3"
+ [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
+ (umod:TI (match_operand:TI 1 "gpc_reg_operand" "v")
+ (match_operand:TI 2 "gpc_reg_operand" "v")))]
+ "TARGET_POWER10"
+ "vmoduq %0,%1,%2"
+ [(set_attr "type" "vecdiv")])
+
;; Logical instructions
;; The logical instructions are mostly combined by using match_operator,
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