[gcc r8-10562] AArch64: Add prefer_advsimd_autovec internal tune_flag

[Kyrylo Tkachov]

https://gcc.gnu.org/g:42140cb640bd8ab9362d89b8ab01f31309069710

commit r8-10562-g42140cb640bd8ab9362d89b8ab01f31309069710
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu Oct 1 17:36:13 2020 +0100

    AArch64: Add prefer_advsimd_autovec internal tune_flag
    
    This is the GCC 8 version of the prefer_advsimd_autovec patch.
    It's very similar to the GCC 9 version.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    gcc/
            * config/aarch64/aarch64-tuning-flags.def
            (PREFER_ADVSIMD_AUTOVEC): Define.
            * config/aarch64/aarch64.c (aarch64_preferred_simd_mode): Use
            it.
            (aarch64_autovectorize_vector_sizes): Likewise.

Diff:
---
 gcc/config/aarch64/aarch64-tuning-flags.def |  3 +++
 gcc/config/aarch64/aarch64.c                | 13 +++++++++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def
index ea9ead234cb..0f242630f46 100644
--- a/gcc/config/aarch64/aarch64-tuning-flags.def
+++ b/gcc/config/aarch64/aarch64-tuning-flags.def
@@ -41,4 +41,7 @@ AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW)
    are not considered cheap.  */
 AARCH64_EXTRA_TUNING_OPTION ("cheap_shift_extend", CHEAP_SHIFT_EXTEND)
 
+/* Prefer Advanced SIMD over SVE for auto-vectorization.  */
+AARCH64_EXTRA_TUNING_OPTION ("prefer_advsimd_autovec", PREFER_ADVSIMD_AUTOVEC)
+
 #undef AARCH64_EXTRA_TUNING_OPTION
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index e20a4ccc6dc..6c05a6686c5 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -12970,7 +12970,12 @@ aarch64_simd_container_mode (scalar_mode mode, poly_int64 width)
 static machine_mode
 aarch64_preferred_simd_mode (scalar_mode mode)
 {
-  poly_int64 bits = TARGET_SVE ? BITS_PER_SVE_VECTOR : 128;
+  /* If current tuning prefers Advanced SIMD, bypass SVE.  */
+  bool use_sve
+    = TARGET_SVE
+      && !(aarch64_tune_params.extra_tuning_flags
+	   & AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC);
+  poly_int64 bits = use_sve ? BITS_PER_SVE_VECTOR : 128;
   return aarch64_simd_container_mode (mode, bits);
 }
 
@@ -12979,7 +12984,11 @@ aarch64_preferred_simd_mode (scalar_mode mode)
 static void
 aarch64_autovectorize_vector_sizes (vector_sizes *sizes)
 {
-  if (TARGET_SVE)
+  bool use_sve
+    = TARGET_SVE
+      && !(aarch64_tune_params.extra_tuning_flags
+	   & AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC);
+  if (use_sve)
     sizes->safe_push (BYTES_PER_SVE_VECTOR);
   sizes->safe_push (16);
   sizes->safe_push (8);