[gcc(refs/vendors/AWS/heads/Arm64/gcc-7-branch)] [AArch64] Add support for Neoverse N1

[Sebastian Pop]

https://gcc.gnu.org/g:6ea080762f71e3e49583086b83a7849317355536

commit 6ea080762f71e3e49583086b83a7849317355536
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri Feb 22 08:56:50 2019 +0000

    [AArch64] Add support for Neoverse N1
    
    This patch adds support for the Neoverse N1 CPU [1]. This was supported in GCC earlier through the codename Ares,
    which it now replaces. -mcpu=ares is still accepted as there's been a binutils release supporting it,
    but the internal structures are renamed to use Neoverse N1-related identifiers.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    
    2019-02-22  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
    
    gcc/
            * config/aarch64/aarch64.c (ares_tunings): Rename to...
            (neoversen1_tunings): ... This.
            * config/aarch64/aarch64-cores.def (ares): Change tuning to the above.
            (neoverse-n1): New CPU.
            * config/aarch64/aarch64-tune.md: Regenerate.
            * doc/invoke.txt (AArch64 Options): Document neoverse-n1.
    
    (cherry picked from commit 9ed6834deacecd0e0671793e1440aa728939b93f)

Diff:
---
 gcc/config/aarch64/aarch64-cores.def | 3 ++-
 gcc/config/aarch64/aarch64-tune.md   | 2 +-
 gcc/config/aarch64/aarch64.c         | 2 +-
 gcc/doc/invoke.texi                  | 1 +
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index cd16b2bd0df..4bf0813f0e0 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -84,6 +84,7 @@ AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8A,  AARCH
 AARCH64_CORE("cortex-a72.cortex-a53",  cortexa72cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, 0x41, AARCH64_BIG_LITTLE (0xd08, 0xd03), -1)
 AARCH64_CORE("cortex-a73.cortex-a35",  cortexa73cortexa35, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd04), -1)
 AARCH64_CORE("cortex-a73.cortex-a53",  cortexa73cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd03), -1)
-AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16, ares, 0x41, 0xd0c, -1)
+AARCH64_CORE("ares",  ares, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16, neoversen1, 0x41, 0xd0c, -1)
+AARCH64_CORE("neoverse-n1",  neoversen1, cortexa57, 8_2A,  AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16, neoversen1, 0x41, 0xd0c, -1)
 
 #undef AARCH64_CORE
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index c948846af7e..8efbe9cb029 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr "tune"
-	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,falkor,qdf24xx,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,thunderx2t99,xgene1,thunderx2t99p1,vulcan,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
+	"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,exynosm1,falkor,qdf24xx,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,thunderx2t99,xgene1,thunderx2t99p1,vulcan,ares,neoversen1,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
 	(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index bc323450713..2f173919303 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -807,7 +807,7 @@ static const struct tune_params thunderx2t99_tunings =
   (AARCH64_EXTRA_TUNE_NONE)	/* tune_flags.  */
 };
 
-static const struct tune_params ares_tunings =
+static const struct tune_params neoversen1_tunings =
 {
   &cortexa57_extra_costs,
   &generic_addrcost_table,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 8f279e454b0..d941c7b1ed4 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13996,6 +13996,7 @@ Specify the name of the target processor for which GCC should tune the
 performance of the code.  Permissible values for this option are:
 @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
 @samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1}, @samp{falkor},
+@samp{ares}, @samp{neoverse-n1},
 @samp{qdf24xx}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
 @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
 @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},