[gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: veor

[Christophe Lyon]

https://gcc.gnu.org/g:ac173689e62cbf6858bc916eddd577f69a55b5b7

commit ac173689e62cbf6858bc916eddd577f69a55b5b7
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Nov 13 13:05:43 2020 +0000

    arm: Auto-vectorization for MVE: veor
    
    This patch enables MVE veor instructions for auto-vectorization.  MVE
    veor insns in mve.md are modified to use xor instead of unspec
    expression to support xor<mode>3.  The xor<mode>3 expander is added to
    vec-common.md
    
    2020-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/
            * config/arm/mve.md (mve_veorq_s<mode>): New entry for veor
            instruction using expression xor.
            (mve_veorq_u<mode>): Likewise.
            * config/arm/neon.md (xor<mode>3): Renamed into xor<mode>3_neon.
            * config/arm/vec-common.md (xor<mode>3): New expander.
    
            gcc/testsuite/
            * gcc.target/arm/simd/mve-vlogical_1.c: Add tests for veor.

Diff:
---
 gcc/config/arm/mve.md                            | 19 +++++++---
 gcc/config/arm/neon.md                           |  2 +-
 gcc/config/arm/vec-common.md                     |  9 ++++-
 gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c | 44 ++++++++++++++++++++++++
 4 files changed, 67 insertions(+), 7 deletions(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 4127236c4f7..4c6cc093822 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1203,15 +1203,24 @@
 ;;
 ;; [veorq_u, veorq_s])
 ;;
-(define_insn "mve_veorq_<supf><mode>"
+(define_insn "mve_veorq_s<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VEORQ))
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "veor %q0, %q1, %q2"
+  "veor\t%q0, %q1, %q2"
+  [(set_attr "type" "mve_move")
+])
+(define_insn "mve_veorq_u<mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+	(xor:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
+  ]
+  "TARGET_HAVE_MVE"
+  "veor\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 669c34da4e0..e1263b00b39 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -747,7 +747,7 @@
   [(set_attr "type" "neon_logic<q>")]
 )
 
-(define_insn "xor<mode>3"
+(define_insn "xor<mode>3_neon"
   [(set (match_operand:VDQ 0 "s_register_operand" "=w")
 	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "w")
 		 (match_operand:VDQ 2 "s_register_operand" "w")))]
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 3e8387c54cb..99ea1cc0b06 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -185,4 +185,11 @@
 	(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "")
 		 (match_operand:VDQ 2 "neon_logic_op2" "")))]
   "TARGET_NEON || TARGET_HAVE_MVE"
-)
\ No newline at end of file
+)
+
+(define_expand "xor<mode>3"
+  [(set (match_operand:VDQ 0 "s_register_operand" "")
+	(xor:VDQ (match_operand:VDQ 1 "s_register_operand" "")
+		 (match_operand:VDQ 2 "s_register_operand" "")))]
+  "TARGET_NEON || TARGET_HAVE_MVE"
+)
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c b/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
index 903604fdd12..4e9ed6e1c53 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
@@ -92,3 +92,47 @@ void test_vorr_i8_u (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
 }
 
 /* { dg-final { scan-assembler-times {vorr\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */
+
+void test_veor_i32 (int32_t * __restrict__ dest, int32_t * a, int32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i32_u (uint32_t * __restrict__ dest, uint32_t * a, uint32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16 (int16_t * __restrict__ dest, int16_t * a, int16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i16_u (uint16_t * __restrict__ dest, uint16_t * a, uint16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8 (int8_t * __restrict__ dest, int8_t * a, int8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+void test_veor_i8_u (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] ^ b[i];
+  }
+}
+
+/* { dg-final { scan-assembler-times {veor\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */