[gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: vorr

[Christophe Lyon]

https://gcc.gnu.org/g:1e6af3cc196d3c3443eccccd9a97526c4459bd73

commit 1e6af3cc196d3c3443eccccd9a97526c4459bd73
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Fri Nov 13 12:34:12 2020 +0000

    arm: Auto-vectorization for MVE: vorr
    
    This patch enables MVE vorr instructions for auto-vectorization.  MVE
    vorr insns in mve.md are modified to use ior instead of unspec
    expression to support ior<mode>3.  The ior<mode>3 expander is added to
    vec-common.md
    
    2020-11-13  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/
            * config/arm/mve.md (mve_vorrq_s<mode>): New entry for vorr
            instruction using expression ior.
            (mve_vorrq_u<mode>): Likewise.
            * config/arm/neon.md (ior<mode>3): Renamed into ior<mode>3_neon.
            * config/arm/vec-common.md (ior<mode>3): New expander.
    
            gcc/testsuite/
            * gcc.target/arm/simd/mve-vlogical_1.c: Add vorr tests.

Diff:
---
 gcc/config/arm/mve.md                            | 19 +++++++---
 gcc/config/arm/neon.md                           |  2 +-
 gcc/config/arm/vec-common.md                     |  7 ++++
 gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c | 44 ++++++++++++++++++++++++
 4 files changed, 66 insertions(+), 6 deletions(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 2309f125a5e..4127236c4f7 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1609,15 +1609,24 @@
 ;;
 ;; [vorrq_s, vorrq_u])
 ;;
-(define_insn "mve_vorrq_<supf><mode>"
+(define_insn "mve_vorrq_s<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VORRQ))
+	(ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vorr %q0, %q1, %q2"
+  "vorr\t%q0, %q1, %q2"
+  [(set_attr "type" "mve_move")
+])
+(define_insn "mve_vorrq_u<mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+	(ior:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
+  ]
+  "TARGET_HAVE_MVE"
+  "vorr\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index dc4707d7447..669c34da4e0 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -690,7 +690,7 @@
    (set_attr "predicable" "no")]
 )
 
-(define_insn "ior<mode>3"
+(define_insn "ior<mode>3_neon"
   [(set (match_operand:VDQ 0 "s_register_operand" "=w,w")
 	(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0")
 		 (match_operand:VDQ 2 "neon_logic_op2" "w,Dl")))]
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index cbc9e25acbc..3e8387c54cb 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -179,3 +179,10 @@
 		 (match_operand:VDQ 2 "neon_inv_logic_op2" "")))]
   "TARGET_NEON || TARGET_HAVE_MVE"
 )
+
+(define_expand "ior<mode>3"
+  [(set (match_operand:VDQ 0 "s_register_operand" "")
+	(ior:VDQ (match_operand:VDQ 1 "s_register_operand" "")
+		 (match_operand:VDQ 2 "neon_logic_op2" "")))]
+  "TARGET_NEON || TARGET_HAVE_MVE"
+)
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c b/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
index 2665c8086b6..903604fdd12 100644
--- a/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
@@ -48,3 +48,47 @@ void test_vand_i8_u (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
 }
 
 /* { dg-final { scan-assembler-times {vand\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */
+
+void test_vorr_i32 (int32_t * __restrict__ dest, int32_t * a, int32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] | b[i];
+  }
+}
+
+void test_vorr_i32_u (uint32_t * __restrict__ dest, uint32_t * a, uint32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] | b[i];
+  }
+}
+
+void test_vorr_i16 (int16_t * __restrict__ dest, int16_t * a, int16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] | b[i];
+  }
+}
+
+void test_vorr_i16_u (uint16_t * __restrict__ dest, uint16_t * a, uint16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] | b[i];
+  }
+}
+
+void test_vorr_i8 (int8_t * __restrict__ dest, int8_t * a, int8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] | b[i];
+  }
+}
+
+void test_vorr_i8_u (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] | b[i];
+  }
+}
+
+/* { dg-final { scan-assembler-times {vorr\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */