[gcc(refs/users/clyon/heads/mve-autovec)] arm: Auto-vectorization for MVE: vand

[Christophe Lyon]

https://gcc.gnu.org/g:a62ae1e2ba88189e55399134c5043ef6c3c6e35b

commit a62ae1e2ba88189e55399134c5043ef6c3c6e35b
Author: Christophe Lyon <christophe.lyon@linaro.org>
Date:   Thu Nov 12 20:16:05 2020 +0000

    arm: Auto-vectorization for MVE: vand
    
    This patch enables MVE vand instructions for auto-vectorization.  MVE
    vand insns in mve.md are modified to use 'and' instead of unspec
    expression to support and<mode>3.  The and<mode>3 expander is added to
    vec-common.md
    
    2020-11-12  Christophe Lyon  <christophe.lyon@linaro.org>
    
            gcc/
            * config/arm/mve.md (mve_vandq_s<mode>): New entry for vand
            instruction using expression and.
            (mve_vandq_u<mode>): Likewise.
            * config/arm/neon.md (and<mode>3): Renamed into and<mode>3_neon.
            * config/arm/vec-common.md (and<mode>3): New expander.
    
            gcc/testsuite/
            * gcc.target/arm/simd/mve-vlogical_1.c: New test.

Diff:
---
 gcc/config/arm/mve.md                            | 19 ++++++---
 gcc/config/arm/neon.md                           |  2 +-
 gcc/config/arm/vec-common.md                     |  7 ++++
 gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c | 50 ++++++++++++++++++++++++
 4 files changed, 72 insertions(+), 6 deletions(-)

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index ecbaaa91501..2309f125a5e 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -894,15 +894,24 @@
 ;;
 ;; [vandq_u, vandq_s])
 ;;
-(define_insn "mve_vandq_<supf><mode>"
+(define_insn "mve_vandq_s<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VANDQ))
+	(and:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
-  "vand %q0, %q1, %q2"
+  "vand\t%q0, %q1, %q2"
+  [(set_attr "type" "mve_move")
+])
+(define_insn "mve_vandq_u<mode>"
+  [
+   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
+	(and:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")
+		       (match_operand:MVE_2 2 "s_register_operand" "w")))
+  ]
+  "TARGET_HAVE_MVE"
+  "vand\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 2d767698378..dc4707d7447 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -712,7 +712,7 @@
 ;; corresponds to the canonical form the middle-end expects to use for
 ;; immediate bitwise-ANDs.
 
-(define_insn "and<mode>3"
+(define_insn "and<mode>3_neon"
   [(set (match_operand:VDQ 0 "s_register_operand" "=w,w")
 	(and:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0")
 		 (match_operand:VDQ 2 "neon_inv_logic_op2" "w,DL")))]
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 250e503876a..cbc9e25acbc 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -172,3 +172,10 @@
 					       GEN_INT (elem), operands[0]));
   DONE;
 })
+
+(define_expand "and<mode>3"
+  [(set (match_operand:VDQ 0 "s_register_operand" "")
+	(and:VDQ (match_operand:VDQ 1 "s_register_operand" "")
+		 (match_operand:VDQ 2 "neon_inv_logic_op2" "")))]
+  "TARGET_NEON || TARGET_HAVE_MVE"
+)
diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c b/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
new file mode 100644
index 00000000000..2665c8086b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vlogical.c
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+
+void test_vand_i32 (int32_t * __restrict__ dest, int32_t * a, int32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] & b[i];
+  }
+}
+
+void test_vand_i32_u (uint32_t * __restrict__ dest, uint32_t * a, uint32_t * b) {
+  int i;
+  for (i=0; i<4; i++) {
+    dest[i] = a[i] & b[i];
+  }
+}
+
+void test_vand_i16 (int16_t * __restrict__ dest, int16_t * a, int16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] & b[i];
+  }
+}
+
+void test_vand_i16_u (uint16_t * __restrict__ dest, uint16_t * a, uint16_t * b) {
+  int i;
+  for (i=0; i<8; i++) {
+    dest[i] = a[i] & b[i];
+  }
+}
+
+void test_vand_i8 (int8_t * __restrict__ dest, int8_t * a, int8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] & b[i];
+  }
+}
+
+void test_vand_i8_u (uint8_t * __restrict__ dest, uint8_t * a, uint8_t * b) {
+  int i;
+  for (i=0; i<16; i++) {
+    dest[i] = a[i] & b[i];
+  }
+}
+
+/* { dg-final { scan-assembler-times {vand\tq[0-9]+, q[0-9]+, q[0-9]+} 6 } } */