[gcc(refs/users/wschmidt/heads/builtins4)] rs6000: Revise altivec.h to use rs6000-vecdefines.h
William Schmidt
wschmidt@gcc.gnu.org
Thu Nov 12 22:32:55 GMT 2020
https://gcc.gnu.org/g:d436e8286edad1f0c4e8dc255954d7b98dfbecf8
commit d436e8286edad1f0c4e8dc255954d7b98dfbecf8
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Thu Nov 12 17:32:28 2020 -0500
rs6000: Revise altivec.h to use rs6000-vecdefines.h
2020-11-12 Bill Schmidt <wschmidt@linux.ibm.com>
* config/rs6000/altivec.h: Remove almost all #define's, including
many that are deprecated; #include rs6000-vecdefines.h.
* config/rs6000/rs6000-gen-builtins.c (write_defines_file): Add
one-time inclusion support.
* config/rs6000/rs6000-overload.def: Add overloads I missed
before.
* config/rs6000/t-rs6000: Add EXTRA_HEADERS and a rule for
rs6000-vecdefines.h.
Diff:
---
gcc/config/rs6000/altivec.h | 483 +-------------------------------
gcc/config/rs6000/rs6000-gen-builtins.c | 3 +
gcc/config/rs6000/rs6000-overload.def | 158 ++++++++---
gcc/config/rs6000/t-rs6000 | 9 +
4 files changed, 140 insertions(+), 513 deletions(-)
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index df10a8c498d..cfaf4fe2de8 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -55,295 +55,13 @@
#define __CR6_LT 2
#define __CR6_LT_REV 3
-/* Synonyms. */
-#define vec_vaddcuw vec_addc
-#define vec_vand vec_and
-#define vec_vandc vec_andc
-#define vec_vrfip vec_ceil
-#define vec_vcmpbfp vec_cmpb
-#define vec_vcmpgefp vec_cmpge
-#define vec_vctsxs vec_cts
-#define vec_vctuxs vec_ctu
-#define vec_vexptefp vec_expte
-#define vec_vrfim vec_floor
-#define vec_lvx vec_ld
-#define vec_lvxl vec_ldl
-#define vec_vlogefp vec_loge
-#define vec_vmaddfp vec_madd
-#define vec_vmhaddshs vec_madds
-#define vec_vmladduhm vec_mladd
-#define vec_vmhraddshs vec_mradds
-#define vec_vnmsubfp vec_nmsub
-#define vec_vnor vec_nor
-#define vec_vor vec_or
-#define vec_vpkpx vec_packpx
-#define vec_vperm vec_perm
-#define vec_permxor __builtin_vec_vpermxor
-#define vec_vrefp vec_re
-#define vec_vrfin vec_round
-#define vec_vrsqrtefp vec_rsqrte
-#define vec_vsel vec_sel
-#define vec_vsldoi vec_sld
-#define vec_vsl vec_sll
-#define vec_vslo vec_slo
-#define vec_vspltisb vec_splat_s8
-#define vec_vspltish vec_splat_s16
-#define vec_vspltisw vec_splat_s32
-#define vec_vsr vec_srl
-#define vec_vsro vec_sro
-#define vec_stvx vec_st
-#define vec_stvxl vec_stl
-#define vec_vsubcuw vec_subc
-#define vec_vsum2sws vec_sum2s
-#define vec_vsumsws vec_sums
-#define vec_vrfiz vec_trunc
-#define vec_vxor vec_xor
+#include "rs6000-vecdefines.h"
+/* Synonyms. */
/* Functions that are resolved by the backend to one of the
typed builtins. */
-#define vec_vaddfp __builtin_vec_vaddfp
-#define vec_addc __builtin_vec_addc
-#define vec_adde __builtin_vec_adde
-#define vec_addec __builtin_vec_addec
-#define vec_vaddsws __builtin_vec_vaddsws
-#define vec_vaddshs __builtin_vec_vaddshs
-#define vec_vaddsbs __builtin_vec_vaddsbs
-#define vec_vavgsw __builtin_vec_vavgsw
-#define vec_vavguw __builtin_vec_vavguw
-#define vec_vavgsh __builtin_vec_vavgsh
-#define vec_vavguh __builtin_vec_vavguh
-#define vec_vavgsb __builtin_vec_vavgsb
-#define vec_vavgub __builtin_vec_vavgub
-#define vec_ceil __builtin_vec_ceil
-#define vec_cmpb __builtin_vec_cmpb
-#define vec_vcmpeqfp __builtin_vec_vcmpeqfp
-#define vec_cmpge __builtin_vec_cmpge
-#define vec_vcmpgtfp __builtin_vec_vcmpgtfp
-#define vec_vcmpgtsw __builtin_vec_vcmpgtsw
-#define vec_vcmpgtuw __builtin_vec_vcmpgtuw
-#define vec_vcmpgtsh __builtin_vec_vcmpgtsh
-#define vec_vcmpgtuh __builtin_vec_vcmpgtuh
-#define vec_vcmpgtsb __builtin_vec_vcmpgtsb
-#define vec_vcmpgtub __builtin_vec_vcmpgtub
-#define vec_vcfsx __builtin_vec_vcfsx
-#define vec_vcfux __builtin_vec_vcfux
-#define vec_cts __builtin_vec_cts
-#define vec_ctu __builtin_vec_ctu
-#define vec_cpsgn __builtin_vec_copysign
-#define vec_double __builtin_vec_double
-#define vec_doublee __builtin_vec_doublee
-#define vec_doubleo __builtin_vec_doubleo
-#define vec_doublel __builtin_vec_doublel
-#define vec_doubleh __builtin_vec_doubleh
-#define vec_expte __builtin_vec_expte
-#define vec_float __builtin_vec_float
-#define vec_float2 __builtin_vec_float2
-#define vec_floate __builtin_vec_floate
-#define vec_floato __builtin_vec_floato
-#define vec_floor __builtin_vec_floor
-#define vec_loge __builtin_vec_loge
-#define vec_madd __builtin_vec_madd
-#define vec_madds __builtin_vec_madds
-#define vec_mtvscr __builtin_vec_mtvscr
-#define vec_reve __builtin_vec_vreve
-#define vec_vmaxfp __builtin_vec_vmaxfp
-#define vec_vmaxsw __builtin_vec_vmaxsw
-#define vec_vmaxsh __builtin_vec_vmaxsh
-#define vec_vmaxsb __builtin_vec_vmaxsb
-#define vec_vminfp __builtin_vec_vminfp
-#define vec_vminsw __builtin_vec_vminsw
-#define vec_vminsh __builtin_vec_vminsh
-#define vec_vminsb __builtin_vec_vminsb
-#define vec_mradds __builtin_vec_mradds
-#define vec_vmsumshm __builtin_vec_vmsumshm
-#define vec_vmsumuhm __builtin_vec_vmsumuhm
-#define vec_vmsummbm __builtin_vec_vmsummbm
-#define vec_vmsumubm __builtin_vec_vmsumubm
-#define vec_vmsumshs __builtin_vec_vmsumshs
-#define vec_vmsumuhs __builtin_vec_vmsumuhs
-#define vec_vmsumudm __builtin_vec_vmsumudm
-#define vec_vmulesb __builtin_vec_vmulesb
-#define vec_vmulesh __builtin_vec_vmulesh
-#define vec_vmuleuh __builtin_vec_vmuleuh
-#define vec_vmuleub __builtin_vec_vmuleub
-#define vec_vmulosh __builtin_vec_vmulosh
-#define vec_vmulouh __builtin_vec_vmulouh
-#define vec_vmulosb __builtin_vec_vmulosb
-#define vec_vmuloub __builtin_vec_vmuloub
-#define vec_nmsub __builtin_vec_nmsub
-#define vec_packpx __builtin_vec_packpx
-#define vec_vpkswss __builtin_vec_vpkswss
-#define vec_vpkuwus __builtin_vec_vpkuwus
-#define vec_vpkshss __builtin_vec_vpkshss
-#define vec_vpkuhus __builtin_vec_vpkuhus
-#define vec_vpkswus __builtin_vec_vpkswus
-#define vec_vpkshus __builtin_vec_vpkshus
-#define vec_re __builtin_vec_re
-#define vec_round __builtin_vec_round
-#define vec_recipdiv __builtin_vec_recipdiv
-#define vec_rlmi __builtin_vec_rlmi
-#define vec_vrlnm __builtin_vec_rlnm
#define vec_rlnm(a,b,c) (__builtin_vec_rlnm((a),((c)<<8)|(b)))
-#define vec_rsqrt __builtin_vec_rsqrt
-#define vec_rsqrte __builtin_vec_rsqrte
-#define vec_signed __builtin_vec_vsigned
-#define vec_signed2 __builtin_vec_vsigned2
-#define vec_signede __builtin_vec_vsignede
-#define vec_signedo __builtin_vec_vsignedo
-#define vec_unsigned __builtin_vec_vunsigned
-#define vec_unsigned2 __builtin_vec_vunsigned2
-#define vec_unsignede __builtin_vec_vunsignede
-#define vec_unsignedo __builtin_vec_vunsignedo
-#define vec_vsubfp __builtin_vec_vsubfp
-#define vec_subc __builtin_vec_subc
-#define vec_sube __builtin_vec_sube
-#define vec_subec __builtin_vec_subec
-#define vec_vsubsws __builtin_vec_vsubsws
-#define vec_vsubshs __builtin_vec_vsubshs
-#define vec_vsubsbs __builtin_vec_vsubsbs
-#define vec_sum4s __builtin_vec_sum4s
-#define vec_vsum4shs __builtin_vec_vsum4shs
-#define vec_vsum4sbs __builtin_vec_vsum4sbs
-#define vec_vsum4ubs __builtin_vec_vsum4ubs
-#define vec_sum2s __builtin_vec_sum2s
-#define vec_sums __builtin_vec_sums
-#define vec_trunc __builtin_vec_trunc
-#define vec_vupkhpx __builtin_vec_vupkhpx
-#define vec_vupkhsh __builtin_vec_vupkhsh
-#define vec_vupkhsb __builtin_vec_vupkhsb
-#define vec_vupklpx __builtin_vec_vupklpx
-#define vec_vupklsh __builtin_vec_vupklsh
-#define vec_vupklsb __builtin_vec_vupklsb
-#define vec_abs __builtin_vec_abs
-#define vec_nabs __builtin_vec_nabs
-#define vec_abss __builtin_vec_abss
-#define vec_add __builtin_vec_add
-#define vec_adds __builtin_vec_adds
-#define vec_and __builtin_vec_and
-#define vec_andc __builtin_vec_andc
-#define vec_avg __builtin_vec_avg
-#define vec_cmpeq __builtin_vec_cmpeq
-#define vec_cmpne __builtin_vec_cmpne
-#define vec_cmpgt __builtin_vec_cmpgt
-#define vec_ctf __builtin_vec_ctf
-#define vec_dst __builtin_vec_dst
-#define vec_dstst __builtin_vec_dstst
-#define vec_dststt __builtin_vec_dststt
-#define vec_dstt __builtin_vec_dstt
-#define vec_ld __builtin_vec_ld
-#define vec_lde __builtin_vec_lde
-#define vec_ldl __builtin_vec_ldl
-#define vec_lvebx __builtin_vec_lvebx
-#define vec_lvehx __builtin_vec_lvehx
-#define vec_lvewx __builtin_vec_lvewx
-#define vec_xl_zext __builtin_vec_ze_lxvrx
-#define vec_xl_sext __builtin_vec_se_lxvrx
-#define vec_xst_trunc __builtin_vec_tr_stxvrx
-#define vec_neg __builtin_vec_neg
-#define vec_pmsum_be __builtin_vec_vpmsum
-#define vec_shasigma_be __builtin_crypto_vshasigma
-/* Cell only intrinsics. */
-#ifdef __PPU__
-#define vec_lvlx __builtin_vec_lvlx
-#define vec_lvlxl __builtin_vec_lvlxl
-#define vec_lvrx __builtin_vec_lvrx
-#define vec_lvrxl __builtin_vec_lvrxl
-#endif
-#define vec_lvsl __builtin_vec_lvsl
-#define vec_lvsr __builtin_vec_lvsr
-#define vec_max __builtin_vec_max
-#define vec_mergee __builtin_vec_vmrgew
-#define vec_mergeh __builtin_vec_mergeh
-#define vec_mergel __builtin_vec_mergel
-#define vec_mergeo __builtin_vec_vmrgow
-#define vec_min __builtin_vec_min
-#define vec_mladd __builtin_vec_mladd
-#define vec_msum __builtin_vec_msum
-#define vec_msums __builtin_vec_msums
#define vec_mul __builtin_vec_mul
-#define vec_mule __builtin_vec_mule
-#define vec_mulo __builtin_vec_mulo
-#define vec_nor __builtin_vec_nor
-#define vec_or __builtin_vec_or
-#define vec_pack __builtin_vec_pack
-#define vec_packs __builtin_vec_packs
-#define vec_packsu __builtin_vec_packsu
-#define vec_perm __builtin_vec_perm
-#define vec_rl __builtin_vec_rl
-#define vec_sel __builtin_vec_sel
-#define vec_sl __builtin_vec_sl
-#define vec_sld __builtin_vec_sld
-#define vec_sldw __builtin_vsx_xxsldwi
-#define vec_sll __builtin_vec_sll
-#define vec_slo __builtin_vec_slo
-#define vec_splat __builtin_vec_splat
-#define vec_sr __builtin_vec_sr
-#define vec_sra __builtin_vec_sra
-#define vec_srl __builtin_vec_srl
-#define vec_sro __builtin_vec_sro
-#define vec_st __builtin_vec_st
-#define vec_ste __builtin_vec_ste
-#define vec_stl __builtin_vec_stl
-#define vec_stvebx __builtin_vec_stvebx
-#define vec_stvehx __builtin_vec_stvehx
-#define vec_stvewx __builtin_vec_stvewx
-/* Cell only intrinsics. */
-#ifdef __PPU__
-#define vec_stvlx __builtin_vec_stvlx
-#define vec_stvlxl __builtin_vec_stvlxl
-#define vec_stvrx __builtin_vec_stvrx
-#define vec_stvrxl __builtin_vec_stvrxl
-#endif
-#define vec_sub __builtin_vec_sub
-#define vec_subs __builtin_vec_subs
-#define vec_sum __builtin_vec_sum
-#define vec_unpackh __builtin_vec_unpackh
-#define vec_unpackl __builtin_vec_unpackl
-#define vec_vaddubm __builtin_vec_vaddubm
-#define vec_vaddubs __builtin_vec_vaddubs
-#define vec_vadduhm __builtin_vec_vadduhm
-#define vec_vadduhs __builtin_vec_vadduhs
-#define vec_vadduwm __builtin_vec_vadduwm
-#define vec_vadduws __builtin_vec_vadduws
-#define vec_vcmpequb __builtin_vec_vcmpequb
-#define vec_vcmpequh __builtin_vec_vcmpequh
-#define vec_vcmpequw __builtin_vec_vcmpequw
-#define vec_vmaxub __builtin_vec_vmaxub
-#define vec_vmaxuh __builtin_vec_vmaxuh
-#define vec_vmaxuw __builtin_vec_vmaxuw
-#define vec_vminub __builtin_vec_vminub
-#define vec_vminuh __builtin_vec_vminuh
-#define vec_vminuw __builtin_vec_vminuw
-#define vec_vmrghb __builtin_vec_vmrghb
-#define vec_vmrghh __builtin_vec_vmrghh
-#define vec_vmrghw __builtin_vec_vmrghw
-#define vec_vmrglb __builtin_vec_vmrglb
-#define vec_vmrglh __builtin_vec_vmrglh
-#define vec_vmrglw __builtin_vec_vmrglw
-#define vec_vpkuhum __builtin_vec_vpkuhum
-#define vec_vpkuwum __builtin_vec_vpkuwum
-#define vec_vrlb __builtin_vec_vrlb
-#define vec_vrlh __builtin_vec_vrlh
-#define vec_vrlw __builtin_vec_vrlw
-#define vec_vslb __builtin_vec_vslb
-#define vec_vslh __builtin_vec_vslh
-#define vec_vslw __builtin_vec_vslw
-#define vec_vspltb __builtin_vec_vspltb
-#define vec_vsplth __builtin_vec_vsplth
-#define vec_vspltw __builtin_vec_vspltw
-#define vec_vsrab __builtin_vec_vsrab
-#define vec_vsrah __builtin_vec_vsrah
-#define vec_vsraw __builtin_vec_vsraw
-#define vec_vsrb __builtin_vec_vsrb
-#define vec_vsrh __builtin_vec_vsrh
-#define vec_vsrw __builtin_vec_vsrw
-#define vec_vsububs __builtin_vec_vsububs
-#define vec_vsububm __builtin_vec_vsububm
-#define vec_vsubuhm __builtin_vec_vsubuhm
-#define vec_vsubuhs __builtin_vec_vsubuhs
-#define vec_vsubuwm __builtin_vec_vsubuwm
-#define vec_vsubuws __builtin_vec_vsubuws
-#define vec_xor __builtin_vec_xor
#define vec_extract __builtin_vec_extract
#define vec_insert __builtin_vec_insert
@@ -352,151 +70,8 @@
#ifdef __VSX__
/* VSX additions */
-#define vec_div __builtin_vec_div
-#define vec_mul __builtin_vec_mul
-#define vec_msub __builtin_vec_msub
-#define vec_nmadd __builtin_vec_nmadd
-#define vec_nearbyint __builtin_vec_nearbyint
-#define vec_rint __builtin_vec_rint
-#define vec_sqrt __builtin_vec_sqrt
#define vec_vsx_ld __builtin_vec_vsx_ld
#define vec_vsx_st __builtin_vec_vsx_st
-#define vec_xl __builtin_vec_vsx_ld
-#define vec_xl_be __builtin_vec_xl_be
-#define vec_xst __builtin_vec_vsx_st
-#define vec_xst_be __builtin_vec_xst_be
-
-/* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions
- instead of __builtin_vec_<xxx> */
-#define vec_xxsldwi __builtin_vsx_xxsldwi
-#define vec_xxpermdi __builtin_vsx_xxpermdi
-#endif
-
-#ifdef _ARCH_PWR8
-/* Vector additions added in ISA 2.07. */
-#define vec_eqv __builtin_vec_eqv
-#define vec_nand __builtin_vec_nand
-#define vec_orc __builtin_vec_orc
-#define vec_vaddcuq __builtin_vec_vaddcuq
-#define vec_vaddudm __builtin_vec_vaddudm
-#define vec_vadduqm __builtin_vec_vadduqm
-#define vec_vbpermq __builtin_vec_vbpermq
-#define vec_bperm __builtin_vec_vbperm_api
-#define vec_vclz __builtin_vec_vclz
-#define vec_cntlz __builtin_vec_vclz
-#define vec_vclzb __builtin_vec_vclzb
-#define vec_vclzd __builtin_vec_vclzd
-#define vec_vclzh __builtin_vec_vclzh
-#define vec_vclzw __builtin_vec_vclzw
-#define vec_vaddecuq __builtin_vec_vaddecuq
-#define vec_vaddeuqm __builtin_vec_vaddeuqm
-#define vec_vsubecuq __builtin_vec_vsubecuq
-#define vec_vsubeuqm __builtin_vec_vsubeuqm
-#define vec_vgbbd __builtin_vec_vgbbd
-#define vec_gb __builtin_vec_vgbbd
-#define vec_vmaxsd __builtin_vec_vmaxsd
-#define vec_vmaxud __builtin_vec_vmaxud
-#define vec_vminsd __builtin_vec_vminsd
-#define vec_vminud __builtin_vec_vminud
-#define vec_vmrgew __builtin_vec_vmrgew
-#define vec_vmrgow __builtin_vec_vmrgow
-#define vec_vpksdss __builtin_vec_vpksdss
-#define vec_vpksdus __builtin_vec_vpksdus
-#define vec_vpkudum __builtin_vec_vpkudum
-#define vec_vpkudus __builtin_vec_vpkudus
-#define vec_vpopcnt __builtin_vec_vpopcnt
-#define vec_vpopcntb __builtin_vec_vpopcntb
-#define vec_vpopcntd __builtin_vec_vpopcntd
-#define vec_vpopcnth __builtin_vec_vpopcnth
-#define vec_vpopcntw __builtin_vec_vpopcntw
-#define vec_popcnt __builtin_vec_vpopcntu
-#define vec_vrld __builtin_vec_vrld
-#define vec_vsld __builtin_vec_vsld
-#define vec_vsrad __builtin_vec_vsrad
-#define vec_vsrd __builtin_vec_vsrd
-#define vec_vsubcuq __builtin_vec_vsubcuq
-#define vec_vsubudm __builtin_vec_vsubudm
-#define vec_vsubuqm __builtin_vec_vsubuqm
-#define vec_vupkhsw __builtin_vec_vupkhsw
-#define vec_vupklsw __builtin_vec_vupklsw
-#define vec_revb __builtin_vec_revb
-#define vec_sbox_be __builtin_crypto_vsbox_be
-#define vec_cipher_be __builtin_crypto_vcipher_be
-#define vec_cipherlast_be __builtin_crypto_vcipherlast_be
-#define vec_ncipher_be __builtin_crypto_vncipher_be
-#define vec_ncipherlast_be __builtin_crypto_vncipherlast_be
-#endif
-
-#ifdef __POWER9_VECTOR__
-/* Vector additions added in ISA 3.0. */
-#define vec_first_match_index __builtin_vec_first_match_index
-#define vec_first_match_or_eos_index __builtin_vec_first_match_or_eos_index
-#define vec_first_mismatch_index __builtin_vec_first_mismatch_index
-#define vec_first_mismatch_or_eos_index __builtin_vec_first_mismatch_or_eos_index
-#define vec_pack_to_short_fp32 __builtin_vec_convert_4f32_8f16
-#define vec_parity_lsbb __builtin_vec_vparity_lsbb
-#define vec_vctz __builtin_vec_vctz
-#define vec_cnttz __builtin_vec_vctz
-#define vec_vctzb __builtin_vec_vctzb
-#define vec_vctzd __builtin_vec_vctzd
-#define vec_vctzh __builtin_vec_vctzh
-#define vec_vctzw __builtin_vec_vctzw
-#define vec_extract4b __builtin_vec_extract4b
-#define vec_insert4b __builtin_vec_insert4b
-#define vec_vprtyb __builtin_vec_vprtyb
-#define vec_vprtybd __builtin_vec_vprtybd
-#define vec_vprtybw __builtin_vec_vprtybw
-
-#ifdef _ARCH_PPC64
-#define vec_vprtybq __builtin_vec_vprtybq
-#endif
-
-#define vec_absd __builtin_vec_vadu
-#define vec_absdb __builtin_vec_vadub
-#define vec_absdh __builtin_vec_vaduh
-#define vec_absdw __builtin_vec_vaduw
-
-#define vec_slv __builtin_vec_vslv
-#define vec_srv __builtin_vec_vsrv
-
-#define vec_extract_exp __builtin_vec_extract_exp
-#define vec_extract_sig __builtin_vec_extract_sig
-#define vec_insert_exp __builtin_vec_insert_exp
-#define vec_test_data_class __builtin_vec_test_data_class
-
-#define vec_extract_fp_from_shorth __builtin_vec_vextract_fp_from_shorth
-#define vec_extract_fp_from_shortl __builtin_vec_vextract_fp_from_shortl
-#define vec_extract_fp32_from_shorth __builtin_vec_vextract_fp_from_shorth
-#define vec_extract_fp32_from_shortl __builtin_vec_vextract_fp_from_shortl
-
-#define scalar_extract_exp __builtin_vec_scalar_extract_exp
-#define scalar_extract_sig __builtin_vec_scalar_extract_sig
-#define scalar_insert_exp __builtin_vec_scalar_insert_exp
-#define scalar_test_data_class __builtin_vec_scalar_test_data_class
-#define scalar_test_neg __builtin_vec_scalar_test_neg
-
-#define scalar_cmp_exp_gt __builtin_vec_scalar_cmp_exp_gt
-#define scalar_cmp_exp_lt __builtin_vec_scalar_cmp_exp_lt
-#define scalar_cmp_exp_eq __builtin_vec_scalar_cmp_exp_eq
-#define scalar_cmp_exp_unordered __builtin_vec_scalar_cmp_exp_unordered
-
-#ifdef _ARCH_PPC64
-#define vec_xl_len __builtin_vec_lxvl
-#define vec_xst_len __builtin_vec_stxvl
-#define vec_xl_len_r __builtin_vec_xl_len_r
-#define vec_xst_len_r __builtin_vec_xst_len_r
-#endif
-
-#define vec_cmpnez __builtin_vec_vcmpnez
-
-#define vec_cntlz_lsbb __builtin_vec_vclzlsbb
-#define vec_cnttz_lsbb __builtin_vec_vctzlsbb
-
-#define vec_test_lsbb_all_ones __builtin_vec_xvtlsbb_all_ones
-#define vec_test_lsbb_all_zeros __builtin_vec_xvtlsbb_all_zeros
-
-#define vec_xlx __builtin_vec_vextulx
-#define vec_xrx __builtin_vec_vexturx
#endif
/* Predicates.
@@ -673,14 +248,9 @@ __altivec_scalar_pred(vec_any_nle,
#define vec_any_nle(a1, a2) __builtin_vec_vcmpge_p (__CR6_LT_REV, (a2), (a1))
#endif
-/* These do not accept vectors, so they do not have a __builtin_vec_*
- counterpart. */
+/* Miscellaneous definitions. */
#define vec_dss(x) __builtin_altivec_dss((x))
#define vec_dssall() __builtin_altivec_dssall ()
-#define vec_mfvscr() ((__vector unsigned short) __builtin_altivec_mfvscr ())
-#define vec_splat_s8(x) __builtin_altivec_vspltisb ((x))
-#define vec_splat_s16(x) __builtin_altivec_vspltish ((x))
-#define vec_splat_s32(x) __builtin_altivec_vspltisw ((x))
#define vec_splat_u8(x) ((__vector unsigned char) vec_splat_s8 ((x)))
#define vec_splat_u16(x) ((__vector unsigned short) vec_splat_s16 ((x)))
#define vec_splat_u32(x) ((__vector unsigned int) vec_splat_s32 ((x)))
@@ -689,51 +259,4 @@ __altivec_scalar_pred(vec_any_nle,
to #define vec_step to __builtin_vec_step. */
#define vec_step(x) __builtin_vec_step (* (__typeof__ (x) *) 0)
-#ifdef _ARCH_PWR10
-/* May modify these macro definitions if future capabilities overload
- with support for different vector argument and result types. */
-#define vec_cntlzm(a, b) __builtin_altivec_vclzdm (a, b)
-#define vec_cnttzm(a, b) __builtin_altivec_vctzdm (a, b)
-#define vec_pdep(a, b) __builtin_altivec_vpdepd (a, b)
-#define vec_pext(a, b) __builtin_altivec_vpextd (a, b)
-#define vec_cfuge(a, b) __builtin_altivec_vcfuged (a, b)
-#define vec_genpcvm(a, b) __builtin_vec_xxgenpcvm (a, b)
-
-/* Overloaded built-in functions for ISA 3.1. */
-#define vec_extractl(a, b, c) __builtin_vec_extractl (a, b, c)
-#define vec_extracth(a, b, c) __builtin_vec_extracth (a, b, c)
-#define vec_insertl(a, b, c) __builtin_vec_insertl (a, b, c)
-#define vec_inserth(a, b, c) __builtin_vec_inserth (a, b, c)
-#define vec_replace_elt(a, b, c) __builtin_vec_replace_elt (a, b, c)
-#define vec_replace_unaligned(a, b, c) __builtin_vec_replace_un (a, b, c)
-#define vec_sldb(a, b, c) __builtin_vec_sldb (a, b, c)
-#define vec_srdb(a, b, c) __builtin_vec_srdb (a, b, c)
-#define vec_splati(a) __builtin_vec_xxspltiw (a)
-#define vec_splatid(a) __builtin_vec_xxspltid (a)
-#define vec_splati_ins(a, b, c) __builtin_vec_xxsplti32dx (a, b, c)
-#define vec_blendv(a, b, c) __builtin_vec_xxblend (a, b, c)
-#define vec_permx(a, b, c, d) __builtin_vec_xxpermx (a, b, c, d)
-
-#define vec_gnb(a, b) __builtin_vec_gnb (a, b)
-#define vec_clrl(a, b) __builtin_vec_clrl (a, b)
-#define vec_clrr(a, b) __builtin_vec_clrr (a, b)
-#define vec_ternarylogic(a, b, c, d) __builtin_vec_xxeval (a, b, c, d)
-
-#define vec_strir(a) __builtin_vec_strir (a)
-#define vec_stril(a) __builtin_vec_stril (a)
-
-#define vec_strir_p(a) __builtin_vec_strir_p (a)
-#define vec_stril_p(a) __builtin_vec_stril_p (a)
-
-/* VSX Mask Manipulation builtin. */
-#define vec_genbm __builtin_vec_mtvsrbm
-#define vec_genhm __builtin_vec_mtvsrhm
-#define vec_genwm __builtin_vec_mtvsrwm
-#define vec_gendm __builtin_vec_mtvsrdm
-#define vec_genqm __builtin_vec_mtvsrqm
-#define vec_cntm __builtin_vec_cntm
-#define vec_expandm __builtin_vec_vexpandm
-#define vec_extractm __builtin_vec_vextractm
-#endif
-
#endif /* _ALTIVEC_H */
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.c b/gcc/config/rs6000/rs6000-gen-builtins.c
index b44abf37e15..c3d828c9451 100644
--- a/gcc/config/rs6000/rs6000-gen-builtins.c
+++ b/gcc/config/rs6000/rs6000-gen-builtins.c
@@ -2678,6 +2678,8 @@ write_init_file ()
static int
write_defines_file ()
{
+ fprintf (defines_file, "#ifndef _RS6000_VECDEFINES_H\n");
+ fprintf (defines_file, "#define _RS6000_VECDEFINES_H 1\n\n");
for (int i = 0; i < num_ovld_stanzas; i++)
if (strcmp (ovld_stanzas[i].extern_name, "SKIP"))
{
@@ -2689,6 +2691,7 @@ write_defines_file ()
if (ovld_stanzas[i].ifdef)
fprintf (defines_file, "#endif\n");
}
+ fprintf (defines_file, "\n#endif\n");
return 1;
}
diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 82037644157..2104da7c3f5 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -166,6 +166,18 @@
vuq __builtin_vec_addc (vuq, vuq);
VADDCUQ VADDCUQ_VUQ
+; TODO: Note that the entry for VEC_ADDE currently gets ignored in
+; altivec_resolve_overloaded_builtin. There are also forms for
+; vsi and vui arguments, but rather than building a define_expand
+; for the instruction sequence generated for those, we do some RTL
+; hackery. Revisit whether we can remove that. For now, keep this
+; much of the entry here to generate the #define, at least.
+[VEC_ADDE, vec_adde, __builtin_vec_adde]
+ vsq __builtin_vec_adde (vsq, vsq, vsq);
+ VADDEUQM VADDEUQM_VSQ
+ vuq __builtin_vec_adde (vuq, vuq, vuq);
+ VADDEUQM VADDEUQM_VUQ
+
; TODO: Note that the entry for VEC_ADDEC currently gets ignored in
; altivec_resolve_overloaded_builtin. There are also forms for
; vsi and vui arguments, but rather than building a define_expand
@@ -192,6 +204,36 @@
vsi __builtin_vec_adds (vsi, vsi);
VADDSWS
+[VEC_AND, vec_and, __builtin_vec_and]
+ vsc __builtin_vec_and (vsc, vsc);
+ VAND_V16QI
+ vuc __builtin_vec_and (vuc, vuc);
+ VAND_V16QI_UNS VAND_VUC
+ vbc __builtin_vec_and (vbc, vbc);
+ VAND_V16QI_UNS VAND_VBC
+ vss __builtin_vec_and (vss, vss);
+ VAND_V8HI
+ vus __builtin_vec_and (vus, vus);
+ VAND_V8HI_UNS VAND_VUS
+ vbs __builtin_vec_and (vbs, vbs);
+ VAND_V8HI_UNS VAND_VBS
+ vsi __builtin_vec_and (vsi, vsi);
+ VAND_V4SI
+ vui __builtin_vec_and (vui, vui);
+ VAND_V4SI_UNS VAND_VUI
+ vbi __builtin_vec_and (vbi, vbi);
+ VAND_V4SI_UNS VAND_VBI
+ vsll __builtin_vec_and (vsll, vsll);
+ VAND_V2DI
+ vull __builtin_vec_and (vull, vull);
+ VAND_V2DI_UNS VAND_VULL
+ vbll __builtin_vec_and (vbll, vbll);
+ VAND_V2DI_UNS VAND_VBLL
+ vf __builtin_vec_and (vf, vf);
+ VAND_V4SF
+ vd __builtin_vec_and (vd, vd);
+ VAND_V2DF
+
[VEC_ANDC, vec_andc, __builtin_vec_andc]
vbc __builtin_vec_andc (vbc, vbc);
VANDC_V16QI_UNS VANDC_VBC
@@ -987,6 +1029,9 @@
signed int __builtin_vec_vextractm (vuq);
VEXTRACTMQ
+; There is no entry for vec_extract. There is special handling for
+; this in altivec_resolve_overloaded_builtin in rs6000.c.
+
[VEC_EXTRACT_FP_FROM_SHORTH, vec_extract_fp32_from_shorth, __builtin_vec_vextract_fp_from_shorth, _ARCH_PWR9]
vf __builtin_vec_vextract_fp_from_shorth (vus);
VEXTRACT_FP_FROM_SHORTH
@@ -1189,6 +1234,9 @@
vull __builtin_vec_gnb (vuq, unsigned char);
VGNB
+; There is no entry for vec_insert. There is special handling for
+; this in altivec_resolve_overloaded_builtin in rs6000.c.
+
[VEC_INSERTH, vec_inserth, __builtin_vec_inserth, _ARCH_PWR10]
vuc __builtin_vec_inserth (unsigned char, vuc, unsigned int);
VINSERTGPRBR
@@ -1697,6 +1745,10 @@
vd __builtin_vec_vmrgow (vd, vd);
VMRGOW_V2DF
+[VEC_MFVSCR, vec_mfvscr, __builtin_vec_mfvscr]
+ vus __builtin_vec_mfvscr ();
+ MFVSCR
+
[VEC_MIN, vec_min, __builtin_vec_min]
vsc __builtin_vec_min (vsc, vsc);
VMINSB
@@ -2015,18 +2067,32 @@
[VEC_PACKS, vec_packs, __builtin_vec_packs]
vuc __builtin_vec_packs (vus, vus);
- VPKUHUS
+ VPKUHUS VPKUHUS_S
vsc __builtin_vec_packs (vss, vss);
VPKSHSS
vus __builtin_vec_packs (vui, vui);
- VPKUWUS
+ VPKUWUS VPKUWUS_S
vss __builtin_vec_packs (vsi, vsi);
VPKSWSS
vui __builtin_vec_packs (vull, vull);
- VPKUDUS
+ VPKUDUS VPKUDUS_S
vsi __builtin_vec_packs (vsll, vsll);
VPKSDSS
+[VEC_PACKSU, vec_packsu, __builtin_vec_packsu]
+ vuc __builtin_vec_packsu (vus, vus);
+ VPKUHUS VPKUHUS_U
+ vuc __builtin_vec_packsu (vss, vss);
+ VPKSHUS
+ vus __builtin_vec_packsu (vui, vui);
+ VPKUWUS VPKUWUS_U
+ vus __builtin_vec_packsu (vsi, vsi);
+ VPKSWUS
+ vui __builtin_vec_packsu (vull, vull);
+ VPKUDUS VPKUDUS_U
+ vui __builtin_vec_packsu (vsll, vsll);
+ VPKSDUS
+
[VEC_PDEP, vec_pdep, __builtin_vec_vpdepd, _ARCH_PWR10]
vull __builtin_vec_vpdepd (vull, vull);
VPDEPD
@@ -2139,6 +2205,9 @@
vuq __builtin_vec_vparity_lsbb (vuq);
VPRTYBQ VPRTYBQ_U
+; There is no entry for vec_promote. There is special handling for
+; this in altivec_resolve_overloaded_builtin in rs6000.c.
+
[VEC_RE, vec_re, __builtin_vec_re]
vf __builtin_vec_re (vf);
XVRESP
@@ -2261,7 +2330,9 @@
vull __builtin_vec_rlmi (vull, vull, vull);
VRLDMI
-[VEC_RLNM, vec_rlnm, __builtin_vec_rlnm]
+; We SKIP vec_rlnm so that altivec.h can define it as the three-operand
+; form we expose to the users.
+[VEC_RLNM, SKIP, __builtin_vec_rlnm]
vui __builtin_vec_rlnm (vui, vui);
VRLWNM
vull __builtin_vec_rlnm (vull, vull);
@@ -2363,6 +2434,10 @@
vsi __builtin_vec_vsigned2 (vd, vd);
VEC_VSIGNED2_V2DF
+[VEC_SIGNEDE, vec_signede, __builtin_vec_vsignede]
+ vui __builtin_vec_vsignede (vd);
+ VEC_VSIGNEDE_V2DF
+
[VEC_SIGNEDO, vec_signedo, __builtin_vec_vsignedo]
vui __builtin_vec_vsignedo (vd);
VEC_VSIGNEDO_V2DF
@@ -2551,6 +2626,21 @@
vbll __builtin_vec_splat (vbll, signed int);
XXSPLTD_V2DI XXSPLTD_VBLL
+[VEC_SPLAT_S8, vec_splat_s8, __builtin_vec_splat_s8]
+ vsc __builtin_vec_splat_s8 (signed int);
+ VSPLTISB
+
+[VEC_SPLAT_S16, vec_splat_s16, __builtin_vec_splat_s16]
+ vss __builtin_vec_splat_s16 (signed int);
+ VSPLTISH
+
+[VEC_SPLAT_S32, vec_splat_s32, __builtin_vec_splat_s32]
+ vsi __builtin_vec_splat_s32 (signed int);
+ VSPLTISW
+
+; There are no entries for vec_splat_u{8,16,32}. These are handled
+; in altivec.h with a #define and a cast.
+
[VEC_SPLATI, vec_splati, __builtin_vec_xxspltiw, _ARCH_PWR10]
vsi __builtin_vec_xxspltiw (signed int);
VXXSPLTIW_V4SI
@@ -2569,6 +2659,9 @@
vf __builtin_vec_xxsplti32dx (vf, const int, float);
VXXSPLTI32DX_V4SF
+; There is no entry for vec_splats. There is special handling for
+; this in altivec_resolve_overloaded_builtin in rs6000.c.
+
[VEC_SQRT, vec_sqrt, __builtin_vec_sqrt, __VSX__]
vf __builtin_vec_sqrt (vf);
XVSQRTSP
@@ -3117,6 +3210,30 @@
vuq __builtin_vec_subc (vuq, vuq);
VSUBCUQ VSUBCUQ_VUQ
+; TODO: Note that the entry for VEC_SUBE currently gets ignored in
+; altivec_resolve_overloaded_builtin. There are also forms for
+; vsi and vui arguments, but rather than building a define_expand
+; for the instruction sequence generated for those, we do some RTL
+; hackery. Revisit whether we can remove that. For now, keep this
+; much of the entry here to generate the #define, at least.
+[VEC_SUBE, vec_sube, __builtin_vec_sube]
+ vsq __builtin_vec_sube (vsq, vsq, vsq);
+ VSUBEUQM VSUBEUQM_VSQ
+ vuq __builtin_vec_sube (vuq, vuq, vuq);
+ VSUBEUQM VSUBEUQM_VUQ
+
+; TODO: Note that the entry for VEC_SUBEC currently gets ignored in
+; altivec_resolve_overloaded_builtin. There are also forms for
+; vsi and vui arguments, but rather than building a define_expand
+; for the instruction sequence generated for those, we do some RTL
+; hackery. Revisit whether we can remove that. For now, keep this
+; much of the entry here to generate the #define, at least.
+[VEC_SUBEC, vec_subec, __builtin_vec_subec]
+ vsq __builtin_vec_subec (vsq, vsq, vsq);
+ VSUBECUQ VSUBECUQ_VSQ
+ vuq __builtin_vec_subec (vuq, vuq, vuq);
+ VSUBECUQ VSUBECUQ_VUQ
+
[VEC_SUBS, vec_subs, __builtin_vec_subs]
vuc __builtin_vec_subs (vuc, vuc);
VSUBUBS
@@ -3243,39 +3360,14 @@
vsi __builtin_vec_vunsigned2 (vd, vd);
VEC_VUNSIGNED2_V2DF
+[VEC_UNSIGNEDE, vec_unsignede, __builtin_vec_vunsignede]
+ vui __builtin_vec_vunsignede (vd);
+ VEC_VUNSIGNEDE_V2DF
+
[VEC_UNSIGNEDO, vec_unsignedo, __builtin_vec_vunsignedo]
vui __builtin_vec_vunsignedo (vd);
VEC_VUNSIGNEDO_V2DF
-; Not sure this should exist, but it does. This group is redundant with
-; vec_addec, but the next three don't have an alias.
-[VEC_VADDECUQ, vec_vaddecuq, __builtin_vec_vaddecuq]
- vsq __builtin_vec_vaddecuq (vsq, vsq, vsq);
- VADDECUQ VADDECUQ_VSQ2
- vuq __builtin_vec_vaddecuq (vuq, vuq, vuq);
- VADDECUQ VADDECUQ_VUQ2
-
-; Not sure this should exist, but it does.
-[VEC_VADDEUQM, vec_vaddeuqm, __builtin_vec_vaddeuqm]
- vsq __builtin_vec_vaddeuqm (vsq, vsq, vsq);
- VADDEUQM VADDEUQM_VSQ
- vuq __builtin_vec_vaddeuqm (vuq, vuq, vuq);
- VADDEUQM VADDEUQM_VUQ
-
-; Not sure this should exist, but it does.
-[VEC_VSUBECUQ, vec_vsubecuq, __builtin_vec_vsubecuq]
- vsq __builtin_vec_vsubecuq (vsq, vsq, vsq);
- VSUBECUQ VSUBECUQ_VSQ
- vuq __builtin_vec_vsubecuq (vuq, vuq, vuq);
- VSUBECUQ VSUBECUQ_VUQ
-
-; Not sure this should exist, but it does.
-[VEC_VSUBEUQM, vec_vsubeuqm, __builtin_vec_vsubeuqm]
- vsq __builtin_vec_vsubeuqm (vsq, vsq, vsq);
- VSUBEUQM VSUBEUQM_VSQ
- vuq __builtin_vec_vsubeuqm (vuq, vuq, vuq);
- VSUBEUQM VSUBEUQM_VUQ
-
[VEC_VEE, vec_extract_exp, __builtin_vec_extract_exp, _ARCH_PWR9]
vui __builtin_vec_extract_exp (vf);
VEESP
diff --git a/gcc/config/rs6000/t-rs6000 b/gcc/config/rs6000/t-rs6000
index 58a422c4891..2ed15485f4b 100644
--- a/gcc/config/rs6000/t-rs6000
+++ b/gcc/config/rs6000/t-rs6000
@@ -55,6 +55,10 @@ rs6000-gen-builtins: rs6000-gen-builtins.o rbtree.o
$(LINKER_FOR_BUILD) $(BUILD_LINKERFLAGS) $(BUILD_LDFLAGS) -o $@ \
$(filter-out $(BUILD_LIBDEPS), $^) $(BUILD_LIBS)
+# TODO: Whenever GNU make 4.3 is the minimum required, we should us
+# grouped targets on this:
+# rs6000-builtins.c rs6000-builtins.h rs6000-vecdefines.h &: <deps>
+# <recipe>
rs6000-builtins.c: rs6000-gen-builtins \
$(srcdir)/config/rs6000/rs6000-builtin-new.def \
$(srcdir)/config/rs6000/rs6000-overload.def
@@ -62,6 +66,11 @@ rs6000-builtins.c: rs6000-gen-builtins \
$(srcdir)/config/rs6000/rs6000-overload.def rs6000-builtins.h \
rs6000-builtins.c rs6000-vecdefines.h
+# Theoretical race here, but because rs6000-vecdefines.h is only needed
+# at install time, that does not matter in practice.
+EXTRA_HEADERS += rs6000-vecdefines.h
+rs6000-vecdefines.h : rs6000-builtins.c
+
rs6000-builtins.o: rs6000-builtins.c
$(COMPILE) $<
$(POSTCOMPILE)
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