[gcc r11-4805] rs6000: Fix TARGET_POWERPC64 vs. TARGET_64BIT confusion

[Segher Boessenkool]

https://gcc.gnu.org/g:e5502ae72f784470019de5850017ad0c87ffacef

commit r11-4805-ge5502ae72f784470019de5850017ad0c87ffacef
Author: Segher Boessenkool <segher@kernel.crashing.org>
Date:   Fri Nov 6 12:50:35 2020 +0000

    rs6000: Fix TARGET_POWERPC64 vs. TARGET_64BIT confusion
    
    I gave Ke Wen bad advice, luckily David corrected me: it is true that we
    cannot use TARGET_POWERPC64 on many 32-bit OSes, since either the kernel
    or userland does not save the top half of the 64-bit integer registers,
    but we do not have to care about that in separate patterns or related
    code.  The flag is automatically not enabled by default on targets that
    do not handle this correctly.
    
    This patch fixes it.
    
    Segher
    
    2020-11-06  Segher Boessenkool  <segher@kernel.crashing.org>
    
            PR target/96933
            * config/rs6000/rs6000.c (rs6000_expand_vector_init): Use
            TARGET_POWERPC64 instead of TARGET_64BIT.

Diff:
---
 gcc/config/rs6000/rs6000.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index e613353d0c9..63f1c06c01b 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6799,7 +6799,7 @@ rs6000_expand_vector_init (rtx target, rtx vals)
       for (i = 0; i < n_elts; i++)
 	{
 	  rtx tmp = force_reg (GET_MODE_INNER (mode), XVECEXP (vals, 0, i));
-	  if (TARGET_64BIT)
+	  if (TARGET_POWERPC64)
 	    {
 	      op[i] = gen_reg_rtx (DImode);
 	      emit_insn (gen_zero_extendqidi2 (op[i], tmp));
@@ -6909,7 +6909,7 @@ rs6000_expand_vector_init (rtx target, rtx vals)
 	  for (i = 0; i < n_elts; i++)
 	    {
 	      vr_qi[i] = gen_reg_rtx (V16QImode);
-	      if (TARGET_64BIT)
+	      if (TARGET_POWERPC64)
 		emit_insn (gen_p8_mtvsrd_v16qidi2 (vr_qi[i], op[i]));
 	      else
 		emit_insn (gen_p8_mtvsrwz_v16qisi2 (vr_qi[i], op[i]));