[gcc(refs/users/marxin/heads/vect_cond_expr-rework-v3)] i386: Fix ix86_add_reg_usage_to_vzeroupper [PR94308]

[Martin Liska]

https://gcc.gnu.org/g:d5ad8ee04a78b576867fd78b2f25201ea6b4aae1

commit d5ad8ee04a78b576867fd78b2f25201ea6b4aae1
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Wed Mar 25 11:40:00 2020 +0100

    i386: Fix ix86_add_reg_usage_to_vzeroupper [PR94308]
    
    The following patch ICEs due to my recent change r10-6451-gb7b3378f91c.
    Since that patch, for explicit vzeroupper in the sources (when an intrinsic
    is used), we start with the *avx_vzeroupper_1 pattern which contains just the
    UNSPECV_VZEROUPPER and no sets/clobbers.  The vzeroupper pass then adds some
    sets to those, but doesn't add clobbers and finally there is an
    && epilogue_completed splitter that splits this into the *avx_vzeroupper
    pattern which has the right number of sets/clobbers (16 on 64-bit, 8 on
    32-bit) + the UNSPECV_VZEROUPPER first.
    The problem with this testcase on !TARGET_64BIT is that the vzeroupper pass
    adds 8 sets to the pattern, i.e. the maximum number, but INSN_CODE stays
    to be the one of the *avx_vzeroupper_1 pattern.  The splitter doesn't do
    anything here, because it sees the number of rtxes in the PARALLEL already
    the right count, but during final we see that the *avx_vzeroupper_1 pattern
    has "#" output template and ICE that we forgot to split it.
    
    The following patch fixes it by forcing re-recognition of the insn after we
    make the changes to it in ix86_add_reg_usage_to_vzeroupper.  Anything that
    will call recog_memoized later on will recog it and find out it is in this
    case already *avx_vzeroupper rather than *avx_vzeroupper_1.
    
    2020-03-25  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/94308
            * config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
            INSN_CODE (insn) to -1 when changing the pattern.
    
            * gcc.target/i386/pr94308.c: New test.

Diff:
---
 gcc/ChangeLog                           |  6 ++++++
 gcc/config/i386/i386-features.c         |  1 +
 gcc/testsuite/ChangeLog                 |  5 +++++
 gcc/testsuite/gcc.target/i386/pr94308.c | 31 +++++++++++++++++++++++++++++++
 4 files changed, 43 insertions(+)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c63b65a82b0..b2743d65a37 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-25  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94308
+	* config/i386/i386-features.c (ix86_add_reg_usage_to_vzeroupper): Set
+	INSN_CODE (insn) to -1 when changing the pattern.
+
 2020-03-25  Martin Liska  <mliska@suse.cz>
 
 	PR target/93274
diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c
index 3c70279dc7c..66b120d21a7 100644
--- a/gcc/config/i386/i386-features.c
+++ b/gcc/config/i386/i386-features.c
@@ -1792,6 +1792,7 @@ ix86_add_reg_usage_to_vzeroupper (rtx_insn *insn, bitmap live_regs)
       RTVEC_ELT (vec, j) = gen_rtx_SET (reg, reg);
     }
   XVEC (pattern, 0) = vec;
+  INSN_CODE (insn) = -1;
   df_insn_rescan (insn);
 }
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3db4098a8d2..5196036f64a 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-03-25  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/94308
+	* gcc.target/i386/pr94308.c: New test.
+
 2020-03-25  Martin Liska  <mliska@suse.cz>
 
 	PR target/93274
diff --git a/gcc/testsuite/gcc.target/i386/pr94308.c b/gcc/testsuite/gcc.target/i386/pr94308.c
new file mode 100644
index 00000000000..1dcbba94762
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr94308.c
@@ -0,0 +1,31 @@
+/* PR target/94308 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mfpmath=sse -mavx2 -mfma" } */
+
+#include <x86intrin.h>
+
+void
+foo (float *x, const float *y, const float *z, unsigned int w)
+{
+  unsigned int a;
+  const unsigned int b = w / 8;
+  const float *c = y;
+  const float *d = z;
+  __m256 e = _mm256_setzero_ps ();
+  __m256 f, g;
+  for (a = 0; a < b; a++)
+    {
+      f = _mm256_loadu_ps (c);
+      g = _mm256_loadu_ps (d);
+      c += 8;
+      d += 8;
+      e = _mm256_fmadd_ps (f, g, e);
+    }
+  __attribute__ ((aligned (32))) float h[8];
+  _mm256_storeu_ps (h, e);
+  _mm256_zeroupper ();
+  float i = h[0] + h[1] + h[2] + h[3] + h[4] + h[5] + h[6] + h[7];
+  for (a = b * 8; a < w; a++)
+    i += (*c++) * (*d++);
+  *x = i;
+}