[gcc(refs/users/marxin/heads/vect_cond_expr-rework-v3)] [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-care) variant.
Martin Liska
marxin@gcc.gnu.org
Tue Mar 24 14:00:37 GMT 2020
https://gcc.gnu.org/g:261014a1be433a27af75fb7eecc77231261d84f7
commit 261014a1be433a27af75fb7eecc77231261d84f7
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Fri Mar 20 14:14:35 2020 +0000
[ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-care) variant.
This patch supports following MVE ACLE predicated intrinsic with `_x` (dont-care) variant.
* ``_x`` (dont-care) which indicates that the false-predicated lanes have undefined values.
These are syntactic sugar for merge intrinsics with a ``vuninitializedq`` inactive parameter.
vabdq_x_f16, vabdq_x_f32, vabdq_x_s16, vabdq_x_s32, vabdq_x_s8, vabdq_x_u16, vabdq_x_u32, vabdq_x_u8,
vabsq_x_f16, vabsq_x_f32, vabsq_x_s16, vabsq_x_s32, vabsq_x_s8, vaddq_x_f16, vaddq_x_f32, vaddq_x_n_f16,
vaddq_x_n_f32, vaddq_x_n_s16, vaddq_x_n_s32, vaddq_x_n_s8, vaddq_x_n_u16, vaddq_x_n_u32, vaddq_x_n_u8,
vaddq_x_s16, vaddq_x_s32, vaddq_x_s8, vaddq_x_u16, vaddq_x_u32, vaddq_x_u8, vandq_x_f16, vandq_x_f32,
vandq_x_s16, vandq_x_s32, vandq_x_s8, vandq_x_u16, vandq_x_u32, vandq_x_u8, vbicq_x_f16, vbicq_x_f32,
vbicq_x_s16, vbicq_x_s32, vbicq_x_s8, vbicq_x_u16, vbicq_x_u32, vbicq_x_u8, vbrsrq_x_n_f16,
vbrsrq_x_n_f32, vbrsrq_x_n_s16, vbrsrq_x_n_s32, vbrsrq_x_n_s8, vbrsrq_x_n_u16, vbrsrq_x_n_u32,
vbrsrq_x_n_u8, vcaddq_rot270_x_f16, vcaddq_rot270_x_f32, vcaddq_rot270_x_s16, vcaddq_rot270_x_s32,
vcaddq_rot270_x_s8, vcaddq_rot270_x_u16, vcaddq_rot270_x_u32, vcaddq_rot270_x_u8, vcaddq_rot90_x_f16,
vcaddq_rot90_x_f32, vcaddq_rot90_x_s16, vcaddq_rot90_x_s32, vcaddq_rot90_x_s8, vcaddq_rot90_x_u16,
vcaddq_rot90_x_u32, vcaddq_rot90_x_u8, vclsq_x_s16, vclsq_x_s32, vclsq_x_s8, vclzq_x_s16, vclzq_x_s32,
vclzq_x_s8, vclzq_x_u16, vclzq_x_u32, vclzq_x_u8, vcmulq_rot180_x_f16, vcmulq_rot180_x_f32,
vcmulq_rot270_x_f16, vcmulq_rot270_x_f32, vcmulq_rot90_x_f16, vcmulq_rot90_x_f32, vcmulq_x_f16,
vcmulq_x_f32, vcvtaq_x_s16_f16, vcvtaq_x_s32_f32, vcvtaq_x_u16_f16, vcvtaq_x_u32_f32, vcvtbq_x_f32_f16,
vcvtmq_x_s16_f16, vcvtmq_x_s32_f32, vcvtmq_x_u16_f16, vcvtmq_x_u32_f32, vcvtnq_x_s16_f16,
vcvtnq_x_s32_f32, vcvtnq_x_u16_f16, vcvtnq_x_u32_f32, vcvtpq_x_s16_f16, vcvtpq_x_s32_f32,
vcvtpq_x_u16_f16, vcvtpq_x_u32_f32, vcvtq_x_f16_s16, vcvtq_x_f16_u16, vcvtq_x_f32_s32, vcvtq_x_f32_u32,
vcvtq_x_n_f16_s16, vcvtq_x_n_f16_u16, vcvtq_x_n_f32_s32, vcvtq_x_n_f32_u32, vcvtq_x_n_s16_f16,
vcvtq_x_n_s32_f32, vcvtq_x_n_u16_f16, vcvtq_x_n_u32_f32, vcvtq_x_s16_f16, vcvtq_x_s32_f32,
vcvtq_x_u16_f16, vcvtq_x_u32_f32, vcvttq_x_f32_f16, vddupq_x_n_u16, vddupq_x_n_u32, vddupq_x_n_u8,
vddupq_x_wb_u16, vddupq_x_wb_u32, vddupq_x_wb_u8, vdupq_x_n_f16, vdupq_x_n_f32, vdupq_x_n_s16,
vdupq_x_n_s32, vdupq_x_n_s8, vdupq_x_n_u16, vdupq_x_n_u32, vdupq_x_n_u8, vdwdupq_x_n_u16, vdwdupq_x_n_u32,
vdwdupq_x_n_u8, vdwdupq_x_wb_u16, vdwdupq_x_wb_u32, vdwdupq_x_wb_u8, veorq_x_f16, veorq_x_f32, veorq_x_s16,
veorq_x_s32, veorq_x_s8, veorq_x_u16, veorq_x_u32, veorq_x_u8, vhaddq_x_n_s16, vhaddq_x_n_s32,
vhaddq_x_n_s8, vhaddq_x_n_u16, vhaddq_x_n_u32, vhaddq_x_n_u8, vhaddq_x_s16, vhaddq_x_s32, vhaddq_x_s8,
vhaddq_x_u16, vhaddq_x_u32, vhaddq_x_u8, vhcaddq_rot270_x_s16, vhcaddq_rot270_x_s32, vhcaddq_rot270_x_s8,
vhcaddq_rot90_x_s16, vhcaddq_rot90_x_s32, vhcaddq_rot90_x_s8, vhsubq_x_n_s16, vhsubq_x_n_s32,
vhsubq_x_n_s8, vhsubq_x_n_u16, vhsubq_x_n_u32, vhsubq_x_n_u8, vhsubq_x_s16, vhsubq_x_s32, vhsubq_x_s8,
vhsubq_x_u16, vhsubq_x_u32, vhsubq_x_u8, vidupq_x_n_u16, vidupq_x_n_u32, vidupq_x_n_u8, vidupq_x_wb_u16,
vidupq_x_wb_u32, vidupq_x_wb_u8, viwdupq_x_n_u16, viwdupq_x_n_u32, viwdupq_x_n_u8, viwdupq_x_wb_u16,
viwdupq_x_wb_u32, viwdupq_x_wb_u8, vmaxnmq_x_f16, vmaxnmq_x_f32, vmaxq_x_s16, vmaxq_x_s32, vmaxq_x_s8,
vmaxq_x_u16, vmaxq_x_u32, vmaxq_x_u8, vminnmq_x_f16, vminnmq_x_f32, vminq_x_s16, vminq_x_s32, vminq_x_s8,
vminq_x_u16, vminq_x_u32, vminq_x_u8, vmovlbq_x_s16, vmovlbq_x_s8, vmovlbq_x_u16, vmovlbq_x_u8,
vmovltq_x_s16, vmovltq_x_s8, vmovltq_x_u16, vmovltq_x_u8, vmulhq_x_s16, vmulhq_x_s32, vmulhq_x_s8,
vmulhq_x_u16, vmulhq_x_u32, vmulhq_x_u8, vmullbq_int_x_s16, vmullbq_int_x_s32, vmullbq_int_x_s8,
vmullbq_int_x_u16, vmullbq_int_x_u32, vmullbq_int_x_u8, vmullbq_poly_x_p16, vmullbq_poly_x_p8,
vmulltq_int_x_s16, vmulltq_int_x_s32, vmulltq_int_x_s8, vmulltq_int_x_u16, vmulltq_int_x_u32,
vmulltq_int_x_u8, vmulltq_poly_x_p16, vmulltq_poly_x_p8, vmulq_x_f16, vmulq_x_f32, vmulq_x_n_f16,
vmulq_x_n_f32, vmulq_x_n_s16, vmulq_x_n_s32, vmulq_x_n_s8, vmulq_x_n_u16, vmulq_x_n_u32, vmulq_x_n_u8,
vmulq_x_s16, vmulq_x_s32, vmulq_x_s8, vmulq_x_u16, vmulq_x_u32, vmulq_x_u8, vmvnq_x_n_s16, vmvnq_x_n_s32,
vmvnq_x_n_u16, vmvnq_x_n_u32, vmvnq_x_s16, vmvnq_x_s32, vmvnq_x_s8, vmvnq_x_u16, vmvnq_x_u32, vmvnq_x_u8,
vnegq_x_f16, vnegq_x_f32, vnegq_x_s16, vnegq_x_s32, vnegq_x_s8, vornq_x_f16, vornq_x_f32, vornq_x_s16,
vornq_x_s32, vornq_x_s8, vornq_x_u16, vornq_x_u32, vornq_x_u8, vorrq_x_f16, vorrq_x_f32, vorrq_x_s16,
vorrq_x_s32, vorrq_x_s8, vorrq_x_u16, vorrq_x_u32, vorrq_x_u8, vrev16q_x_s8, vrev16q_x_u8, vrev32q_x_f16,
vrev32q_x_s16, vrev32q_x_s8, vrev32q_x_u16, vrev32q_x_u8, vrev64q_x_f16, vrev64q_x_f32, vrev64q_x_s16,
vrev64q_x_s32, vrev64q_x_s8, vrev64q_x_u16, vrev64q_x_u32, vrev64q_x_u8, vrhaddq_x_s16, vrhaddq_x_s32,
vrhaddq_x_s8, vrhaddq_x_u16, vrhaddq_x_u32, vrhaddq_x_u8, vrmulhq_x_s16, vrmulhq_x_s32, vrmulhq_x_s8,
vrmulhq_x_u16, vrmulhq_x_u32, vrmulhq_x_u8, vrndaq_x_f16, vrndaq_x_f32, vrndmq_x_f16, vrndmq_x_f32,
vrndnq_x_f16, vrndnq_x_f32, vrndpq_x_f16, vrndpq_x_f32, vrndq_x_f16, vrndq_x_f32, vrndxq_x_f16,
vrndxq_x_f32, vrshlq_x_s16, vrshlq_x_s32, vrshlq_x_s8, vrshlq_x_u16, vrshlq_x_u32, vrshlq_x_u8,
vrshrq_x_n_s16, vrshrq_x_n_s32, vrshrq_x_n_s8, vrshrq_x_n_u16, vrshrq_x_n_u32, vrshrq_x_n_u8,
vshllbq_x_n_s16, vshllbq_x_n_s8, vshllbq_x_n_u16, vshllbq_x_n_u8, vshlltq_x_n_s16, vshlltq_x_n_s8,
vshlltq_x_n_u16, vshlltq_x_n_u8, vshlq_x_n_s16, vshlq_x_n_s32, vshlq_x_n_s8, vshlq_x_n_u16, vshlq_x_n_u32,
vshlq_x_n_u8, vshlq_x_s16, vshlq_x_s32, vshlq_x_s8, vshlq_x_u16, vshlq_x_u32, vshlq_x_u8, vshrq_x_n_s16,
vshrq_x_n_s32, vshrq_x_n_s8, vshrq_x_n_u16, vshrq_x_n_u32, vshrq_x_n_u8, vsubq_x_f16, vsubq_x_f32,
vsubq_x_n_f16, vsubq_x_n_f32, vsubq_x_n_s16, vsubq_x_n_s32, vsubq_x_n_s8, vsubq_x_n_u16, vsubq_x_n_u32,
vsubq_x_n_u8, vsubq_x_s16, vsubq_x_s32, vsubq_x_s8, vsubq_x_u16, vsubq_x_u32, vsubq_x_u8.
Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details.
[1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics
2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
(vddupq_x_n_u16): Likewise.
(vddupq_x_n_u32): Likewise.
(vddupq_x_wb_u8): Likewise.
(vddupq_x_wb_u16): Likewise.
(vddupq_x_wb_u32): Likewise.
(vdwdupq_x_n_u8): Likewise.
(vdwdupq_x_n_u16): Likewise.
(vdwdupq_x_n_u32): Likewise.
(vdwdupq_x_wb_u8): Likewise.
(vdwdupq_x_wb_u16): Likewise.
(vdwdupq_x_wb_u32): Likewise.
(vidupq_x_n_u8): Likewise.
(vidupq_x_n_u16): Likewise.
(vidupq_x_n_u32): Likewise.
(vidupq_x_wb_u8): Likewise.
(vidupq_x_wb_u16): Likewise.
(vidupq_x_wb_u32): Likewise.
(viwdupq_x_n_u8): Likewise.
(viwdupq_x_n_u16): Likewise.
(viwdupq_x_n_u32): Likewise.
(viwdupq_x_wb_u8): Likewise.
(viwdupq_x_wb_u16): Likewise.
(viwdupq_x_wb_u32): Likewise.
(vdupq_x_n_s8): Likewise.
(vdupq_x_n_s16): Likewise.
(vdupq_x_n_s32): Likewise.
(vdupq_x_n_u8): Likewise.
(vdupq_x_n_u16): Likewise.
(vdupq_x_n_u32): Likewise.
(vminq_x_s8): Likewise.
(vminq_x_s16): Likewise.
(vminq_x_s32): Likewise.
(vminq_x_u8): Likewise.
(vminq_x_u16): Likewise.
(vminq_x_u32): Likewise.
(vmaxq_x_s8): Likewise.
(vmaxq_x_s16): Likewise.
(vmaxq_x_s32): Likewise.
(vmaxq_x_u8): Likewise.
(vmaxq_x_u16): Likewise.
(vmaxq_x_u32): Likewise.
(vabdq_x_s8): Likewise.
(vabdq_x_s16): Likewise.
(vabdq_x_s32): Likewise.
(vabdq_x_u8): Likewise.
(vabdq_x_u16): Likewise.
(vabdq_x_u32): Likewise.
(vabsq_x_s8): Likewise.
(vabsq_x_s16): Likewise.
(vabsq_x_s32): Likewise.
(vaddq_x_s8): Likewise.
(vaddq_x_s16): Likewise.
(vaddq_x_s32): Likewise.
(vaddq_x_n_s8): Likewise.
(vaddq_x_n_s16): Likewise.
(vaddq_x_n_s32): Likewise.
(vaddq_x_u8): Likewise.
(vaddq_x_u16): Likewise.
(vaddq_x_u32): Likewise.
(vaddq_x_n_u8): Likewise.
(vaddq_x_n_u16): Likewise.
(vaddq_x_n_u32): Likewise.
(vclsq_x_s8): Likewise.
(vclsq_x_s16): Likewise.
(vclsq_x_s32): Likewise.
(vclzq_x_s8): Likewise.
(vclzq_x_s16): Likewise.
(vclzq_x_s32): Likewise.
(vclzq_x_u8): Likewise.
(vclzq_x_u16): Likewise.
(vclzq_x_u32): Likewise.
(vnegq_x_s8): Likewise.
(vnegq_x_s16): Likewise.
(vnegq_x_s32): Likewise.
(vmulhq_x_s8): Likewise.
(vmulhq_x_s16): Likewise.
(vmulhq_x_s32): Likewise.
(vmulhq_x_u8): Likewise.
(vmulhq_x_u16): Likewise.
(vmulhq_x_u32): Likewise.
(vmullbq_poly_x_p8): Likewise.
(vmullbq_poly_x_p16): Likewise.
(vmullbq_int_x_s8): Likewise.
(vmullbq_int_x_s16): Likewise.
(vmullbq_int_x_s32): Likewise.
(vmullbq_int_x_u8): Likewise.
(vmullbq_int_x_u16): Likewise.
(vmullbq_int_x_u32): Likewise.
(vmulltq_poly_x_p8): Likewise.
(vmulltq_poly_x_p16): Likewise.
(vmulltq_int_x_s8): Likewise.
(vmulltq_int_x_s16): Likewise.
(vmulltq_int_x_s32): Likewise.
(vmulltq_int_x_u8): Likewise.
(vmulltq_int_x_u16): Likewise.
(vmulltq_int_x_u32): Likewise.
(vmulq_x_s8): Likewise.
(vmulq_x_s16): Likewise.
(vmulq_x_s32): Likewise.
(vmulq_x_n_s8): Likewise.
(vmulq_x_n_s16): Likewise.
(vmulq_x_n_s32): Likewise.
(vmulq_x_u8): Likewise.
(vmulq_x_u16): Likewise.
(vmulq_x_u32): Likewise.
(vmulq_x_n_u8): Likewise.
(vmulq_x_n_u16): Likewise.
(vmulq_x_n_u32): Likewise.
(vsubq_x_s8): Likewise.
(vsubq_x_s16): Likewise.
(vsubq_x_s32): Likewise.
(vsubq_x_n_s8): Likewise.
(vsubq_x_n_s16): Likewise.
(vsubq_x_n_s32): Likewise.
(vsubq_x_u8): Likewise.
(vsubq_x_u16): Likewise.
(vsubq_x_u32): Likewise.
(vsubq_x_n_u8): Likewise.
(vsubq_x_n_u16): Likewise.
(vsubq_x_n_u32): Likewise.
(vcaddq_rot90_x_s8): Likewise.
(vcaddq_rot90_x_s16): Likewise.
(vcaddq_rot90_x_s32): Likewise.
(vcaddq_rot90_x_u8): Likewise.
(vcaddq_rot90_x_u16): Likewise.
(vcaddq_rot90_x_u32): Likewise.
(vcaddq_rot270_x_s8): Likewise.
(vcaddq_rot270_x_s16): Likewise.
(vcaddq_rot270_x_s32): Likewise.
(vcaddq_rot270_x_u8): Likewise.
(vcaddq_rot270_x_u16): Likewise.
(vcaddq_rot270_x_u32): Likewise.
(vhaddq_x_n_s8): Likewise.
(vhaddq_x_n_s16): Likewise.
(vhaddq_x_n_s32): Likewise.
(vhaddq_x_n_u8): Likewise.
(vhaddq_x_n_u16): Likewise.
(vhaddq_x_n_u32): Likewise.
(vhaddq_x_s8): Likewise.
(vhaddq_x_s16): Likewise.
(vhaddq_x_s32): Likewise.
(vhaddq_x_u8): Likewise.
(vhaddq_x_u16): Likewise.
(vhaddq_x_u32): Likewise.
(vhcaddq_rot90_x_s8): Likewise.
(vhcaddq_rot90_x_s16): Likewise.
(vhcaddq_rot90_x_s32): Likewise.
(vhcaddq_rot270_x_s8): Likewise.
(vhcaddq_rot270_x_s16): Likewise.
(vhcaddq_rot270_x_s32): Likewise.
(vhsubq_x_n_s8): Likewise.
(vhsubq_x_n_s16): Likewise.
(vhsubq_x_n_s32): Likewise.
(vhsubq_x_n_u8): Likewise.
(vhsubq_x_n_u16): Likewise.
(vhsubq_x_n_u32): Likewise.
(vhsubq_x_s8): Likewise.
(vhsubq_x_s16): Likewise.
(vhsubq_x_s32): Likewise.
(vhsubq_x_u8): Likewise.
(vhsubq_x_u16): Likewise.
(vhsubq_x_u32): Likewise.
(vrhaddq_x_s8): Likewise.
(vrhaddq_x_s16): Likewise.
(vrhaddq_x_s32): Likewise.
(vrhaddq_x_u8): Likewise.
(vrhaddq_x_u16): Likewise.
(vrhaddq_x_u32): Likewise.
(vrmulhq_x_s8): Likewise.
(vrmulhq_x_s16): Likewise.
(vrmulhq_x_s32): Likewise.
(vrmulhq_x_u8): Likewise.
(vrmulhq_x_u16): Likewise.
(vrmulhq_x_u32): Likewise.
(vandq_x_s8): Likewise.
(vandq_x_s16): Likewise.
(vandq_x_s32): Likewise.
(vandq_x_u8): Likewise.
(vandq_x_u16): Likewise.
(vandq_x_u32): Likewise.
(vbicq_x_s8): Likewise.
(vbicq_x_s16): Likewise.
(vbicq_x_s32): Likewise.
(vbicq_x_u8): Likewise.
(vbicq_x_u16): Likewise.
(vbicq_x_u32): Likewise.
(vbrsrq_x_n_s8): Likewise.
(vbrsrq_x_n_s16): Likewise.
(vbrsrq_x_n_s32): Likewise.
(vbrsrq_x_n_u8): Likewise.
(vbrsrq_x_n_u16): Likewise.
(vbrsrq_x_n_u32): Likewise.
(veorq_x_s8): Likewise.
(veorq_x_s16): Likewise.
(veorq_x_s32): Likewise.
(veorq_x_u8): Likewise.
(veorq_x_u16): Likewise.
(veorq_x_u32): Likewise.
(vmovlbq_x_s8): Likewise.
(vmovlbq_x_s16): Likewise.
(vmovlbq_x_u8): Likewise.
(vmovlbq_x_u16): Likewise.
(vmovltq_x_s8): Likewise.
(vmovltq_x_s16): Likewise.
(vmovltq_x_u8): Likewise.
(vmovltq_x_u16): Likewise.
(vmvnq_x_s8): Likewise.
(vmvnq_x_s16): Likewise.
(vmvnq_x_s32): Likewise.
(vmvnq_x_u8): Likewise.
(vmvnq_x_u16): Likewise.
(vmvnq_x_u32): Likewise.
(vmvnq_x_n_s16): Likewise.
(vmvnq_x_n_s32): Likewise.
(vmvnq_x_n_u16): Likewise.
(vmvnq_x_n_u32): Likewise.
(vornq_x_s8): Likewise.
(vornq_x_s16): Likewise.
(vornq_x_s32): Likewise.
(vornq_x_u8): Likewise.
(vornq_x_u16): Likewise.
(vornq_x_u32): Likewise.
(vorrq_x_s8): Likewise.
(vorrq_x_s16): Likewise.
(vorrq_x_s32): Likewise.
(vorrq_x_u8): Likewise.
(vorrq_x_u16): Likewise.
(vorrq_x_u32): Likewise.
(vrev16q_x_s8): Likewise.
(vrev16q_x_u8): Likewise.
(vrev32q_x_s8): Likewise.
(vrev32q_x_s16): Likewise.
(vrev32q_x_u8): Likewise.
(vrev32q_x_u16): Likewise.
(vrev64q_x_s8): Likewise.
(vrev64q_x_s16): Likewise.
(vrev64q_x_s32): Likewise.
(vrev64q_x_u8): Likewise.
(vrev64q_x_u16): Likewise.
(vrev64q_x_u32): Likewise.
(vrshlq_x_s8): Likewise.
(vrshlq_x_s16): Likewise.
(vrshlq_x_s32): Likewise.
(vrshlq_x_u8): Likewise.
(vrshlq_x_u16): Likewise.
(vrshlq_x_u32): Likewise.
(vshllbq_x_n_s8): Likewise.
(vshllbq_x_n_s16): Likewise.
(vshllbq_x_n_u8): Likewise.
(vshllbq_x_n_u16): Likewise.
(vshlltq_x_n_s8): Likewise.
(vshlltq_x_n_s16): Likewise.
(vshlltq_x_n_u8): Likewise.
(vshlltq_x_n_u16): Likewise.
(vshlq_x_s8): Likewise.
(vshlq_x_s16): Likewise.
(vshlq_x_s32): Likewise.
(vshlq_x_u8): Likewise.
(vshlq_x_u16): Likewise.
(vshlq_x_u32): Likewise.
(vshlq_x_n_s8): Likewise.
(vshlq_x_n_s16): Likewise.
(vshlq_x_n_s32): Likewise.
(vshlq_x_n_u8): Likewise.
(vshlq_x_n_u16): Likewise.
(vshlq_x_n_u32): Likewise.
(vrshrq_x_n_s8): Likewise.
(vrshrq_x_n_s16): Likewise.
(vrshrq_x_n_s32): Likewise.
(vrshrq_x_n_u8): Likewise.
(vrshrq_x_n_u16): Likewise.
(vrshrq_x_n_u32): Likewise.
(vshrq_x_n_s8): Likewise.
(vshrq_x_n_s16): Likewise.
(vshrq_x_n_s32): Likewise.
(vshrq_x_n_u8): Likewise.
(vshrq_x_n_u16): Likewise.
(vshrq_x_n_u32): Likewise.
(vdupq_x_n_f16): Likewise.
(vdupq_x_n_f32): Likewise.
(vminnmq_x_f16): Likewise.
(vminnmq_x_f32): Likewise.
(vmaxnmq_x_f16): Likewise.
(vmaxnmq_x_f32): Likewise.
(vabdq_x_f16): Likewise.
(vabdq_x_f32): Likewise.
(vabsq_x_f16): Likewise.
(vabsq_x_f32): Likewise.
(vaddq_x_f16): Likewise.
(vaddq_x_f32): Likewise.
(vaddq_x_n_f16): Likewise.
(vaddq_x_n_f32): Likewise.
(vnegq_x_f16): Likewise.
(vnegq_x_f32): Likewise.
(vmulq_x_f16): Likewise.
(vmulq_x_f32): Likewise.
(vmulq_x_n_f16): Likewise.
(vmulq_x_n_f32): Likewise.
(vsubq_x_f16): Likewise.
(vsubq_x_f32): Likewise.
(vsubq_x_n_f16): Likewise.
(vsubq_x_n_f32): Likewise.
(vcaddq_rot90_x_f16): Likewise.
(vcaddq_rot90_x_f32): Likewise.
(vcaddq_rot270_x_f16): Likewise.
(vcaddq_rot270_x_f32): Likewise.
(vcmulq_x_f16): Likewise.
(vcmulq_x_f32): Likewise.
(vcmulq_rot90_x_f16): Likewise.
(vcmulq_rot90_x_f32): Likewise.
(vcmulq_rot180_x_f16): Likewise.
(vcmulq_rot180_x_f32): Likewise.
(vcmulq_rot270_x_f16): Likewise.
(vcmulq_rot270_x_f32): Likewise.
(vcvtaq_x_s16_f16): Likewise.
(vcvtaq_x_s32_f32): Likewise.
(vcvtaq_x_u16_f16): Likewise.
(vcvtaq_x_u32_f32): Likewise.
(vcvtnq_x_s16_f16): Likewise.
(vcvtnq_x_s32_f32): Likewise.
(vcvtnq_x_u16_f16): Likewise.
(vcvtnq_x_u32_f32): Likewise.
(vcvtpq_x_s16_f16): Likewise.
(vcvtpq_x_s32_f32): Likewise.
(vcvtpq_x_u16_f16): Likewise.
(vcvtpq_x_u32_f32): Likewise.
(vcvtmq_x_s16_f16): Likewise.
(vcvtmq_x_s32_f32): Likewise.
(vcvtmq_x_u16_f16): Likewise.
(vcvtmq_x_u32_f32): Likewise.
(vcvtbq_x_f32_f16): Likewise.
(vcvttq_x_f32_f16): Likewise.
(vcvtq_x_f16_u16): Likewise.
(vcvtq_x_f16_s16): Likewise.
(vcvtq_x_f32_s32): Likewise.
(vcvtq_x_f32_u32): Likewise.
(vcvtq_x_n_f16_s16): Likewise.
(vcvtq_x_n_f16_u16): Likewise.
(vcvtq_x_n_f32_s32): Likewise.
(vcvtq_x_n_f32_u32): Likewise.
(vcvtq_x_s16_f16): Likewise.
(vcvtq_x_s32_f32): Likewise.
(vcvtq_x_u16_f16): Likewise.
(vcvtq_x_u32_f32): Likewise.
(vcvtq_x_n_s16_f16): Likewise.
(vcvtq_x_n_s32_f32): Likewise.
(vcvtq_x_n_u16_f16): Likewise.
(vcvtq_x_n_u32_f32): Likewise.
(vrndq_x_f16): Likewise.
(vrndq_x_f32): Likewise.
(vrndnq_x_f16): Likewise.
(vrndnq_x_f32): Likewise.
(vrndmq_x_f16): Likewise.
(vrndmq_x_f32): Likewise.
(vrndpq_x_f16): Likewise.
(vrndpq_x_f32): Likewise.
(vrndaq_x_f16): Likewise.
(vrndaq_x_f32): Likewise.
(vrndxq_x_f16): Likewise.
(vrndxq_x_f32): Likewise.
(vandq_x_f16): Likewise.
(vandq_x_f32): Likewise.
(vbicq_x_f16): Likewise.
(vbicq_x_f32): Likewise.
(vbrsrq_x_n_f16): Likewise.
(vbrsrq_x_n_f32): Likewise.
(veorq_x_f16): Likewise.
(veorq_x_f32): Likewise.
(vornq_x_f16): Likewise.
(vornq_x_f32): Likewise.
(vorrq_x_f16): Likewise.
(vorrq_x_f32): Likewise.
(vrev32q_x_f16): Likewise.
(vrev64q_x_f16): Likewise.
(vrev64q_x_f32): Likewise.
(__arm_vddupq_x_n_u8): Define intrinsic.
(__arm_vddupq_x_n_u16): Likewise.
(__arm_vddupq_x_n_u32): Likewise.
(__arm_vddupq_x_wb_u8): Likewise.
(__arm_vddupq_x_wb_u16): Likewise.
(__arm_vddupq_x_wb_u32): Likewise.
(__arm_vdwdupq_x_n_u8): Likewise.
(__arm_vdwdupq_x_n_u16): Likewise.
(__arm_vdwdupq_x_n_u32): Likewise.
(__arm_vdwdupq_x_wb_u8): Likewise.
(__arm_vdwdupq_x_wb_u16): Likewise.
(__arm_vdwdupq_x_wb_u32): Likewise.
(__arm_vidupq_x_n_u8): Likewise.
(__arm_vidupq_x_n_u16): Likewise.
(__arm_vidupq_x_n_u32): Likewise.
(__arm_vidupq_x_wb_u8): Likewise.
(__arm_vidupq_x_wb_u16): Likewise.
(__arm_vidupq_x_wb_u32): Likewise.
(__arm_viwdupq_x_n_u8): Likewise.
(__arm_viwdupq_x_n_u16): Likewise.
(__arm_viwdupq_x_n_u32): Likewise.
(__arm_viwdupq_x_wb_u8): Likewise.
(__arm_viwdupq_x_wb_u16): Likewise.
(__arm_viwdupq_x_wb_u32): Likewise.
(__arm_vdupq_x_n_s8): Likewise.
(__arm_vdupq_x_n_s16): Likewise.
(__arm_vdupq_x_n_s32): Likewise.
(__arm_vdupq_x_n_u8): Likewise.
(__arm_vdupq_x_n_u16): Likewise.
(__arm_vdupq_x_n_u32): Likewise.
(__arm_vminq_x_s8): Likewise.
(__arm_vminq_x_s16): Likewise.
(__arm_vminq_x_s32): Likewise.
(__arm_vminq_x_u8): Likewise.
(__arm_vminq_x_u16): Likewise.
(__arm_vminq_x_u32): Likewise.
(__arm_vmaxq_x_s8): Likewise.
(__arm_vmaxq_x_s16): Likewise.
(__arm_vmaxq_x_s32): Likewise.
(__arm_vmaxq_x_u8): Likewise.
(__arm_vmaxq_x_u16): Likewise.
(__arm_vmaxq_x_u32): Likewise.
(__arm_vabdq_x_s8): Likewise.
(__arm_vabdq_x_s16): Likewise.
(__arm_vabdq_x_s32): Likewise.
(__arm_vabdq_x_u8): Likewise.
(__arm_vabdq_x_u16): Likewise.
(__arm_vabdq_x_u32): Likewise.
(__arm_vabsq_x_s8): Likewise.
(__arm_vabsq_x_s16): Likewise.
(__arm_vabsq_x_s32): Likewise.
(__arm_vaddq_x_s8): Likewise.
(__arm_vaddq_x_s16): Likewise.
(__arm_vaddq_x_s32): Likewise.
(__arm_vaddq_x_n_s8): Likewise.
(__arm_vaddq_x_n_s16): Likewise.
(__arm_vaddq_x_n_s32): Likewise.
(__arm_vaddq_x_u8): Likewise.
(__arm_vaddq_x_u16): Likewise.
(__arm_vaddq_x_u32): Likewise.
(__arm_vaddq_x_n_u8): Likewise.
(__arm_vaddq_x_n_u16): Likewise.
(__arm_vaddq_x_n_u32): Likewise.
(__arm_vclsq_x_s8): Likewise.
(__arm_vclsq_x_s16): Likewise.
(__arm_vclsq_x_s32): Likewise.
(__arm_vclzq_x_s8): Likewise.
(__arm_vclzq_x_s16): Likewise.
(__arm_vclzq_x_s32): Likewise.
(__arm_vclzq_x_u8): Likewise.
(__arm_vclzq_x_u16): Likewise.
(__arm_vclzq_x_u32): Likewise.
(__arm_vnegq_x_s8): Likewise.
(__arm_vnegq_x_s16): Likewise.
(__arm_vnegq_x_s32): Likewise.
(__arm_vmulhq_x_s8): Likewise.
(__arm_vmulhq_x_s16): Likewise.
(__arm_vmulhq_x_s32): Likewise.
(__arm_vmulhq_x_u8): Likewise.
(__arm_vmulhq_x_u16): Likewise.
(__arm_vmulhq_x_u32): Likewise.
(__arm_vmullbq_poly_x_p8): Likewise.
(__arm_vmullbq_poly_x_p16): Likewise.
(__arm_vmullbq_int_x_s8): Likewise.
(__arm_vmullbq_int_x_s16): Likewise.
(__arm_vmullbq_int_x_s32): Likewise.
(__arm_vmullbq_int_x_u8): Likewise.
(__arm_vmullbq_int_x_u16): Likewise.
(__arm_vmullbq_int_x_u32): Likewise.
(__arm_vmulltq_poly_x_p8): Likewise.
(__arm_vmulltq_poly_x_p16): Likewise.
(__arm_vmulltq_int_x_s8): Likewise.
(__arm_vmulltq_int_x_s16): Likewise.
(__arm_vmulltq_int_x_s32): Likewise.
(__arm_vmulltq_int_x_u8): Likewise.
(__arm_vmulltq_int_x_u16): Likewise.
(__arm_vmulltq_int_x_u32): Likewise.
(__arm_vmulq_x_s8): Likewise.
(__arm_vmulq_x_s16): Likewise.
(__arm_vmulq_x_s32): Likewise.
(__arm_vmulq_x_n_s8): Likewise.
(__arm_vmulq_x_n_s16): Likewise.
(__arm_vmulq_x_n_s32): Likewise.
(__arm_vmulq_x_u8): Likewise.
(__arm_vmulq_x_u16): Likewise.
(__arm_vmulq_x_u32): Likewise.
(__arm_vmulq_x_n_u8): Likewise.
(__arm_vmulq_x_n_u16): Likewise.
(__arm_vmulq_x_n_u32): Likewise.
(__arm_vsubq_x_s8): Likewise.
(__arm_vsubq_x_s16): Likewise.
(__arm_vsubq_x_s32): Likewise.
(__arm_vsubq_x_n_s8): Likewise.
(__arm_vsubq_x_n_s16): Likewise.
(__arm_vsubq_x_n_s32): Likewise.
(__arm_vsubq_x_u8): Likewise.
(__arm_vsubq_x_u16): Likewise.
(__arm_vsubq_x_u32): Likewise.
(__arm_vsubq_x_n_u8): Likewise.
(__arm_vsubq_x_n_u16): Likewise.
(__arm_vsubq_x_n_u32): Likewise.
(__arm_vcaddq_rot90_x_s8): Likewise.
(__arm_vcaddq_rot90_x_s16): Likewise.
(__arm_vcaddq_rot90_x_s32): Likewise.
(__arm_vcaddq_rot90_x_u8): Likewise.
(__arm_vcaddq_rot90_x_u16): Likewise.
(__arm_vcaddq_rot90_x_u32): Likewise.
(__arm_vcaddq_rot270_x_s8): Likewise.
(__arm_vcaddq_rot270_x_s16): Likewise.
(__arm_vcaddq_rot270_x_s32): Likewise.
(__arm_vcaddq_rot270_x_u8): Likewise.
(__arm_vcaddq_rot270_x_u16): Likewise.
(__arm_vcaddq_rot270_x_u32): Likewise.
(__arm_vhaddq_x_n_s8): Likewise.
(__arm_vhaddq_x_n_s16): Likewise.
(__arm_vhaddq_x_n_s32): Likewise.
(__arm_vhaddq_x_n_u8): Likewise.
(__arm_vhaddq_x_n_u16): Likewise.
(__arm_vhaddq_x_n_u32): Likewise.
(__arm_vhaddq_x_s8): Likewise.
(__arm_vhaddq_x_s16): Likewise.
(__arm_vhaddq_x_s32): Likewise.
(__arm_vhaddq_x_u8): Likewise.
(__arm_vhaddq_x_u16): Likewise.
(__arm_vhaddq_x_u32): Likewise.
(__arm_vhcaddq_rot90_x_s8): Likewise.
(__arm_vhcaddq_rot90_x_s16): Likewise.
(__arm_vhcaddq_rot90_x_s32): Likewise.
(__arm_vhcaddq_rot270_x_s8): Likewise.
(__arm_vhcaddq_rot270_x_s16): Likewise.
(__arm_vhcaddq_rot270_x_s32): Likewise.
(__arm_vhsubq_x_n_s8): Likewise.
(__arm_vhsubq_x_n_s16): Likewise.
(__arm_vhsubq_x_n_s32): Likewise.
(__arm_vhsubq_x_n_u8): Likewise.
(__arm_vhsubq_x_n_u16): Likewise.
(__arm_vhsubq_x_n_u32): Likewise.
(__arm_vhsubq_x_s8): Likewise.
(__arm_vhsubq_x_s16): Likewise.
(__arm_vhsubq_x_s32): Likewise.
(__arm_vhsubq_x_u8): Likewise.
(__arm_vhsubq_x_u16): Likewise.
(__arm_vhsubq_x_u32): Likewise.
(__arm_vrhaddq_x_s8): Likewise.
(__arm_vrhaddq_x_s16): Likewise.
(__arm_vrhaddq_x_s32): Likewise.
(__arm_vrhaddq_x_u8): Likewise.
(__arm_vrhaddq_x_u16): Likewise.
(__arm_vrhaddq_x_u32): Likewise.
(__arm_vrmulhq_x_s8): Likewise.
(__arm_vrmulhq_x_s16): Likewise.
(__arm_vrmulhq_x_s32): Likewise.
(__arm_vrmulhq_x_u8): Likewise.
(__arm_vrmulhq_x_u16): Likewise.
(__arm_vrmulhq_x_u32): Likewise.
(__arm_vandq_x_s8): Likewise.
(__arm_vandq_x_s16): Likewise.
(__arm_vandq_x_s32): Likewise.
(__arm_vandq_x_u8): Likewise.
(__arm_vandq_x_u16): Likewise.
(__arm_vandq_x_u32): Likewise.
(__arm_vbicq_x_s8): Likewise.
(__arm_vbicq_x_s16): Likewise.
(__arm_vbicq_x_s32): Likewise.
(__arm_vbicq_x_u8): Likewise.
(__arm_vbicq_x_u16): Likewise.
(__arm_vbicq_x_u32): Likewise.
(__arm_vbrsrq_x_n_s8): Likewise.
(__arm_vbrsrq_x_n_s16): Likewise.
(__arm_vbrsrq_x_n_s32): Likewise.
(__arm_vbrsrq_x_n_u8): Likewise.
(__arm_vbrsrq_x_n_u16): Likewise.
(__arm_vbrsrq_x_n_u32): Likewise.
(__arm_veorq_x_s8): Likewise.
(__arm_veorq_x_s16): Likewise.
(__arm_veorq_x_s32): Likewise.
(__arm_veorq_x_u8): Likewise.
(__arm_veorq_x_u16): Likewise.
(__arm_veorq_x_u32): Likewise.
(__arm_vmovlbq_x_s8): Likewise.
(__arm_vmovlbq_x_s16): Likewise.
(__arm_vmovlbq_x_u8): Likewise.
(__arm_vmovlbq_x_u16): Likewise.
(__arm_vmovltq_x_s8): Likewise.
(__arm_vmovltq_x_s16): Likewise.
(__arm_vmovltq_x_u8): Likewise.
(__arm_vmovltq_x_u16): Likewise.
(__arm_vmvnq_x_s8): Likewise.
(__arm_vmvnq_x_s16): Likewise.
(__arm_vmvnq_x_s32): Likewise.
(__arm_vmvnq_x_u8): Likewise.
(__arm_vmvnq_x_u16): Likewise.
(__arm_vmvnq_x_u32): Likewise.
(__arm_vmvnq_x_n_s16): Likewise.
(__arm_vmvnq_x_n_s32): Likewise.
(__arm_vmvnq_x_n_u16): Likewise.
(__arm_vmvnq_x_n_u32): Likewise.
(__arm_vornq_x_s8): Likewise.
(__arm_vornq_x_s16): Likewise.
(__arm_vornq_x_s32): Likewise.
(__arm_vornq_x_u8): Likewise.
(__arm_vornq_x_u16): Likewise.
(__arm_vornq_x_u32): Likewise.
(__arm_vorrq_x_s8): Likewise.
(__arm_vorrq_x_s16): Likewise.
(__arm_vorrq_x_s32): Likewise.
(__arm_vorrq_x_u8): Likewise.
(__arm_vorrq_x_u16): Likewise.
(__arm_vorrq_x_u32): Likewise.
(__arm_vrev16q_x_s8): Likewise.
(__arm_vrev16q_x_u8): Likewise.
(__arm_vrev32q_x_s8): Likewise.
(__arm_vrev32q_x_s16): Likewise.
(__arm_vrev32q_x_u8): Likewise.
(__arm_vrev32q_x_u16): Likewise.
(__arm_vrev64q_x_s8): Likewise.
(__arm_vrev64q_x_s16): Likewise.
(__arm_vrev64q_x_s32): Likewise.
(__arm_vrev64q_x_u8): Likewise.
(__arm_vrev64q_x_u16): Likewise.
(__arm_vrev64q_x_u32): Likewise.
(__arm_vrshlq_x_s8): Likewise.
(__arm_vrshlq_x_s16): Likewise.
(__arm_vrshlq_x_s32): Likewise.
(__arm_vrshlq_x_u8): Likewise.
(__arm_vrshlq_x_u16): Likewise.
(__arm_vrshlq_x_u32): Likewise.
(__arm_vshllbq_x_n_s8): Likewise.
(__arm_vshllbq_x_n_s16): Likewise.
(__arm_vshllbq_x_n_u8): Likewise.
(__arm_vshllbq_x_n_u16): Likewise.
(__arm_vshlltq_x_n_s8): Likewise.
(__arm_vshlltq_x_n_s16): Likewise.
(__arm_vshlltq_x_n_u8): Likewise.
(__arm_vshlltq_x_n_u16): Likewise.
(__arm_vshlq_x_s8): Likewise.
(__arm_vshlq_x_s16): Likewise.
(__arm_vshlq_x_s32): Likewise.
(__arm_vshlq_x_u8): Likewise.
(__arm_vshlq_x_u16): Likewise.
(__arm_vshlq_x_u32): Likewise.
(__arm_vshlq_x_n_s8): Likewise.
(__arm_vshlq_x_n_s16): Likewise.
(__arm_vshlq_x_n_s32): Likewise.
(__arm_vshlq_x_n_u8): Likewise.
(__arm_vshlq_x_n_u16): Likewise.
(__arm_vshlq_x_n_u32): Likewise.
(__arm_vrshrq_x_n_s8): Likewise.
(__arm_vrshrq_x_n_s16): Likewise.
(__arm_vrshrq_x_n_s32): Likewise.
(__arm_vrshrq_x_n_u8): Likewise.
(__arm_vrshrq_x_n_u16): Likewise.
(__arm_vrshrq_x_n_u32): Likewise.
(__arm_vshrq_x_n_s8): Likewise.
(__arm_vshrq_x_n_s16): Likewise.
(__arm_vshrq_x_n_s32): Likewise.
(__arm_vshrq_x_n_u8): Likewise.
(__arm_vshrq_x_n_u16): Likewise.
(__arm_vshrq_x_n_u32): Likewise.
(__arm_vdupq_x_n_f16): Likewise.
(__arm_vdupq_x_n_f32): Likewise.
(__arm_vminnmq_x_f16): Likewise.
(__arm_vminnmq_x_f32): Likewise.
(__arm_vmaxnmq_x_f16): Likewise.
(__arm_vmaxnmq_x_f32): Likewise.
(__arm_vabdq_x_f16): Likewise.
(__arm_vabdq_x_f32): Likewise.
(__arm_vabsq_x_f16): Likewise.
(__arm_vabsq_x_f32): Likewise.
(__arm_vaddq_x_f16): Likewise.
(__arm_vaddq_x_f32): Likewise.
(__arm_vaddq_x_n_f16): Likewise.
(__arm_vaddq_x_n_f32): Likewise.
(__arm_vnegq_x_f16): Likewise.
(__arm_vnegq_x_f32): Likewise.
(__arm_vmulq_x_f16): Likewise.
(__arm_vmulq_x_f32): Likewise.
(__arm_vmulq_x_n_f16): Likewise.
(__arm_vmulq_x_n_f32): Likewise.
(__arm_vsubq_x_f16): Likewise.
(__arm_vsubq_x_f32): Likewise.
(__arm_vsubq_x_n_f16): Likewise.
(__arm_vsubq_x_n_f32): Likewise.
(__arm_vcaddq_rot90_x_f16): Likewise.
(__arm_vcaddq_rot90_x_f32): Likewise.
(__arm_vcaddq_rot270_x_f16): Likewise.
(__arm_vcaddq_rot270_x_f32): Likewise.
(__arm_vcmulq_x_f16): Likewise.
(__arm_vcmulq_x_f32): Likewise.
(__arm_vcmulq_rot90_x_f16): Likewise.
(__arm_vcmulq_rot90_x_f32): Likewise.
(__arm_vcmulq_rot180_x_f16): Likewise.
(__arm_vcmulq_rot180_x_f32): Likewise.
(__arm_vcmulq_rot270_x_f16): Likewise.
(__arm_vcmulq_rot270_x_f32): Likewise.
(__arm_vcvtaq_x_s16_f16): Likewise.
(__arm_vcvtaq_x_s32_f32): Likewise.
(__arm_vcvtaq_x_u16_f16): Likewise.
(__arm_vcvtaq_x_u32_f32): Likewise.
(__arm_vcvtnq_x_s16_f16): Likewise.
(__arm_vcvtnq_x_s32_f32): Likewise.
(__arm_vcvtnq_x_u16_f16): Likewise.
(__arm_vcvtnq_x_u32_f32): Likewise.
(__arm_vcvtpq_x_s16_f16): Likewise.
(__arm_vcvtpq_x_s32_f32): Likewise.
(__arm_vcvtpq_x_u16_f16): Likewise.
(__arm_vcvtpq_x_u32_f32): Likewise.
(__arm_vcvtmq_x_s16_f16): Likewise.
(__arm_vcvtmq_x_s32_f32): Likewise.
(__arm_vcvtmq_x_u16_f16): Likewise.
(__arm_vcvtmq_x_u32_f32): Likewise.
(__arm_vcvtbq_x_f32_f16): Likewise.
(__arm_vcvttq_x_f32_f16): Likewise.
(__arm_vcvtq_x_f16_u16): Likewise.
(__arm_vcvtq_x_f16_s16): Likewise.
(__arm_vcvtq_x_f32_s32): Likewise.
(__arm_vcvtq_x_f32_u32): Likewise.
(__arm_vcvtq_x_n_f16_s16): Likewise.
(__arm_vcvtq_x_n_f16_u16): Likewise.
(__arm_vcvtq_x_n_f32_s32): Likewise.
(__arm_vcvtq_x_n_f32_u32): Likewise.
(__arm_vcvtq_x_s16_f16): Likewise.
(__arm_vcvtq_x_s32_f32): Likewise.
(__arm_vcvtq_x_u16_f16): Likewise.
(__arm_vcvtq_x_u32_f32): Likewise.
(__arm_vcvtq_x_n_s16_f16): Likewise.
(__arm_vcvtq_x_n_s32_f32): Likewise.
(__arm_vcvtq_x_n_u16_f16): Likewise.
(__arm_vcvtq_x_n_u32_f32): Likewise.
(__arm_vrndq_x_f16): Likewise.
(__arm_vrndq_x_f32): Likewise.
(__arm_vrndnq_x_f16): Likewise.
(__arm_vrndnq_x_f32): Likewise.
(__arm_vrndmq_x_f16): Likewise.
(__arm_vrndmq_x_f32): Likewise.
(__arm_vrndpq_x_f16): Likewise.
(__arm_vrndpq_x_f32): Likewise.
(__arm_vrndaq_x_f16): Likewise.
(__arm_vrndaq_x_f32): Likewise.
(__arm_vrndxq_x_f16): Likewise.
(__arm_vrndxq_x_f32): Likewise.
(__arm_vandq_x_f16): Likewise.
(__arm_vandq_x_f32): Likewise.
(__arm_vbicq_x_f16): Likewise.
(__arm_vbicq_x_f32): Likewise.
(__arm_vbrsrq_x_n_f16): Likewise.
(__arm_vbrsrq_x_n_f32): Likewise.
(__arm_veorq_x_f16): Likewise.
(__arm_veorq_x_f32): Likewise.
(__arm_vornq_x_f16): Likewise.
(__arm_vornq_x_f32): Likewise.
(__arm_vorrq_x_f16): Likewise.
(__arm_vorrq_x_f32): Likewise.
(__arm_vrev32q_x_f16): Likewise.
(__arm_vrev64q_x_f16): Likewise.
(__arm_vrev64q_x_f32): Likewise.
(vabdq_x): Define polymorphic variant.
(vabsq_x): Likewise.
(vaddq_x): Likewise.
(vandq_x): Likewise.
(vbicq_x): Likewise.
(vbrsrq_x): Likewise.
(vcaddq_rot270_x): Likewise.
(vcaddq_rot90_x): Likewise.
(vcmulq_rot180_x): Likewise.
(vcmulq_rot270_x): Likewise.
(vcmulq_x): Likewise.
(vcvtq_x): Likewise.
(vcvtq_x_n): Likewise.
(vcvtnq_m): Likewise.
(veorq_x): Likewise.
(vmaxnmq_x): Likewise.
(vminnmq_x): Likewise.
(vmulq_x): Likewise.
(vnegq_x): Likewise.
(vornq_x): Likewise.
(vorrq_x): Likewise.
(vrev32q_x): Likewise.
(vrev64q_x): Likewise.
(vrndaq_x): Likewise.
(vrndmq_x): Likewise.
(vrndnq_x): Likewise.
(vrndpq_x): Likewise.
(vrndq_x): Likewise.
(vrndxq_x): Likewise.
(vsubq_x): Likewise.
(vcmulq_rot90_x): Likewise.
(vadciq): Likewise.
(vclsq_x): Likewise.
(vclzq_x): Likewise.
(vhaddq_x): Likewise.
(vhcaddq_rot270_x): Likewise.
(vhcaddq_rot90_x): Likewise.
(vhsubq_x): Likewise.
(vmaxq_x): Likewise.
(vminq_x): Likewise.
(vmovlbq_x): Likewise.
(vmovltq_x): Likewise.
(vmulhq_x): Likewise.
(vmullbq_int_x): Likewise.
(vmullbq_poly_x): Likewise.
(vmulltq_int_x): Likewise.
(vmulltq_poly_x): Likewise.
(vmvnq_x): Likewise.
(vrev16q_x): Likewise.
(vrhaddq_x): Likewise.
(vrmulhq_x): Likewise.
(vrshlq_x): Likewise.
(vrshrq_x): Likewise.
(vshllbq_x): Likewise.
(vshlltq_x): Likewise.
(vshlq_x_n): Likewise.
(vshlq_x): Likewise.
(vdwdupq_x_u8): Likewise.
(vdwdupq_x_u16): Likewise.
(vdwdupq_x_u32): Likewise.
(viwdupq_x_u8): Likewise.
(viwdupq_x_u16): Likewise.
(viwdupq_x_u32): Likewise.
(vidupq_x_u8): Likewise.
(vddupq_x_u8): Likewise.
(vidupq_x_u16): Likewise.
(vddupq_x_u16): Likewise.
(vidupq_x_u32): Likewise.
(vddupq_x_u32): Likewise.
(vshrq_x): Likewise.
gcc/testsuite/ChangeLog:
2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: New test.
* gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclsq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclsq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclsq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vclzq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
* gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
Diff:
---
gcc/ChangeLog | 825 +++
gcc/config/arm/arm_mve.h | 6025 ++++++++++++++++----
gcc/testsuite/ChangeLog | 378 ++
.../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 24 +
.../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 23 +
.../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 23 +
.../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 23 +
.../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 23 +
.../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 23 +
.../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 23 +
.../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 23 +
.../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 24 +
.../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 23 +
.../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 15 +
.../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 15 +
.../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 15 +
.../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 15 +
.../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 15 +
.../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 15 +
.../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 15 +
.../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 15 +
.../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 15 +
.../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 15 +
.../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 15 +
.../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 15 +
.../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 15 +
.../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 15 +
.../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 15 +
.../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 15 +
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.../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 24 +
.../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 24 +
.../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 24 +
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.../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 15 +
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.../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 24 +
.../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 24 +
.../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 24 +
.../arm/mve/intrinsics/vddupq_x_wb_u16.c | 26 +
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.../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 26 +
.../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 15 +
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.../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 24 +
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.../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 2 +-
.../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 2 +-
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.../arm/mve/intrinsics/vidupq_x_wb_u16.c | 26 +
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.../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 23 +
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.../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 23 +
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.../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 23 +
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.../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 23 +
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.../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 23 +
.../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 23 +
.../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 23 +
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.../arm/mve/intrinsics/vshllbq_x_n_s16.c | 16 +
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.../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 16 +
.../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 16 +
382 files changed, 14292 insertions(+), 1097 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 362345516b8..6bbdf060497 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,828 @@
+2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * config/arm/arm_mve.h (vddupq_x_n_u8): Define macro.
+ (vddupq_x_n_u16): Likewise.
+ (vddupq_x_n_u32): Likewise.
+ (vddupq_x_wb_u8): Likewise.
+ (vddupq_x_wb_u16): Likewise.
+ (vddupq_x_wb_u32): Likewise.
+ (vdwdupq_x_n_u8): Likewise.
+ (vdwdupq_x_n_u16): Likewise.
+ (vdwdupq_x_n_u32): Likewise.
+ (vdwdupq_x_wb_u8): Likewise.
+ (vdwdupq_x_wb_u16): Likewise.
+ (vdwdupq_x_wb_u32): Likewise.
+ (vidupq_x_n_u8): Likewise.
+ (vidupq_x_n_u16): Likewise.
+ (vidupq_x_n_u32): Likewise.
+ (vidupq_x_wb_u8): Likewise.
+ (vidupq_x_wb_u16): Likewise.
+ (vidupq_x_wb_u32): Likewise.
+ (viwdupq_x_n_u8): Likewise.
+ (viwdupq_x_n_u16): Likewise.
+ (viwdupq_x_n_u32): Likewise.
+ (viwdupq_x_wb_u8): Likewise.
+ (viwdupq_x_wb_u16): Likewise.
+ (viwdupq_x_wb_u32): Likewise.
+ (vdupq_x_n_s8): Likewise.
+ (vdupq_x_n_s16): Likewise.
+ (vdupq_x_n_s32): Likewise.
+ (vdupq_x_n_u8): Likewise.
+ (vdupq_x_n_u16): Likewise.
+ (vdupq_x_n_u32): Likewise.
+ (vminq_x_s8): Likewise.
+ (vminq_x_s16): Likewise.
+ (vminq_x_s32): Likewise.
+ (vminq_x_u8): Likewise.
+ (vminq_x_u16): Likewise.
+ (vminq_x_u32): Likewise.
+ (vmaxq_x_s8): Likewise.
+ (vmaxq_x_s16): Likewise.
+ (vmaxq_x_s32): Likewise.
+ (vmaxq_x_u8): Likewise.
+ (vmaxq_x_u16): Likewise.
+ (vmaxq_x_u32): Likewise.
+ (vabdq_x_s8): Likewise.
+ (vabdq_x_s16): Likewise.
+ (vabdq_x_s32): Likewise.
+ (vabdq_x_u8): Likewise.
+ (vabdq_x_u16): Likewise.
+ (vabdq_x_u32): Likewise.
+ (vabsq_x_s8): Likewise.
+ (vabsq_x_s16): Likewise.
+ (vabsq_x_s32): Likewise.
+ (vaddq_x_s8): Likewise.
+ (vaddq_x_s16): Likewise.
+ (vaddq_x_s32): Likewise.
+ (vaddq_x_n_s8): Likewise.
+ (vaddq_x_n_s16): Likewise.
+ (vaddq_x_n_s32): Likewise.
+ (vaddq_x_u8): Likewise.
+ (vaddq_x_u16): Likewise.
+ (vaddq_x_u32): Likewise.
+ (vaddq_x_n_u8): Likewise.
+ (vaddq_x_n_u16): Likewise.
+ (vaddq_x_n_u32): Likewise.
+ (vclsq_x_s8): Likewise.
+ (vclsq_x_s16): Likewise.
+ (vclsq_x_s32): Likewise.
+ (vclzq_x_s8): Likewise.
+ (vclzq_x_s16): Likewise.
+ (vclzq_x_s32): Likewise.
+ (vclzq_x_u8): Likewise.
+ (vclzq_x_u16): Likewise.
+ (vclzq_x_u32): Likewise.
+ (vnegq_x_s8): Likewise.
+ (vnegq_x_s16): Likewise.
+ (vnegq_x_s32): Likewise.
+ (vmulhq_x_s8): Likewise.
+ (vmulhq_x_s16): Likewise.
+ (vmulhq_x_s32): Likewise.
+ (vmulhq_x_u8): Likewise.
+ (vmulhq_x_u16): Likewise.
+ (vmulhq_x_u32): Likewise.
+ (vmullbq_poly_x_p8): Likewise.
+ (vmullbq_poly_x_p16): Likewise.
+ (vmullbq_int_x_s8): Likewise.
+ (vmullbq_int_x_s16): Likewise.
+ (vmullbq_int_x_s32): Likewise.
+ (vmullbq_int_x_u8): Likewise.
+ (vmullbq_int_x_u16): Likewise.
+ (vmullbq_int_x_u32): Likewise.
+ (vmulltq_poly_x_p8): Likewise.
+ (vmulltq_poly_x_p16): Likewise.
+ (vmulltq_int_x_s8): Likewise.
+ (vmulltq_int_x_s16): Likewise.
+ (vmulltq_int_x_s32): Likewise.
+ (vmulltq_int_x_u8): Likewise.
+ (vmulltq_int_x_u16): Likewise.
+ (vmulltq_int_x_u32): Likewise.
+ (vmulq_x_s8): Likewise.
+ (vmulq_x_s16): Likewise.
+ (vmulq_x_s32): Likewise.
+ (vmulq_x_n_s8): Likewise.
+ (vmulq_x_n_s16): Likewise.
+ (vmulq_x_n_s32): Likewise.
+ (vmulq_x_u8): Likewise.
+ (vmulq_x_u16): Likewise.
+ (vmulq_x_u32): Likewise.
+ (vmulq_x_n_u8): Likewise.
+ (vmulq_x_n_u16): Likewise.
+ (vmulq_x_n_u32): Likewise.
+ (vsubq_x_s8): Likewise.
+ (vsubq_x_s16): Likewise.
+ (vsubq_x_s32): Likewise.
+ (vsubq_x_n_s8): Likewise.
+ (vsubq_x_n_s16): Likewise.
+ (vsubq_x_n_s32): Likewise.
+ (vsubq_x_u8): Likewise.
+ (vsubq_x_u16): Likewise.
+ (vsubq_x_u32): Likewise.
+ (vsubq_x_n_u8): Likewise.
+ (vsubq_x_n_u16): Likewise.
+ (vsubq_x_n_u32): Likewise.
+ (vcaddq_rot90_x_s8): Likewise.
+ (vcaddq_rot90_x_s16): Likewise.
+ (vcaddq_rot90_x_s32): Likewise.
+ (vcaddq_rot90_x_u8): Likewise.
+ (vcaddq_rot90_x_u16): Likewise.
+ (vcaddq_rot90_x_u32): Likewise.
+ (vcaddq_rot270_x_s8): Likewise.
+ (vcaddq_rot270_x_s16): Likewise.
+ (vcaddq_rot270_x_s32): Likewise.
+ (vcaddq_rot270_x_u8): Likewise.
+ (vcaddq_rot270_x_u16): Likewise.
+ (vcaddq_rot270_x_u32): Likewise.
+ (vhaddq_x_n_s8): Likewise.
+ (vhaddq_x_n_s16): Likewise.
+ (vhaddq_x_n_s32): Likewise.
+ (vhaddq_x_n_u8): Likewise.
+ (vhaddq_x_n_u16): Likewise.
+ (vhaddq_x_n_u32): Likewise.
+ (vhaddq_x_s8): Likewise.
+ (vhaddq_x_s16): Likewise.
+ (vhaddq_x_s32): Likewise.
+ (vhaddq_x_u8): Likewise.
+ (vhaddq_x_u16): Likewise.
+ (vhaddq_x_u32): Likewise.
+ (vhcaddq_rot90_x_s8): Likewise.
+ (vhcaddq_rot90_x_s16): Likewise.
+ (vhcaddq_rot90_x_s32): Likewise.
+ (vhcaddq_rot270_x_s8): Likewise.
+ (vhcaddq_rot270_x_s16): Likewise.
+ (vhcaddq_rot270_x_s32): Likewise.
+ (vhsubq_x_n_s8): Likewise.
+ (vhsubq_x_n_s16): Likewise.
+ (vhsubq_x_n_s32): Likewise.
+ (vhsubq_x_n_u8): Likewise.
+ (vhsubq_x_n_u16): Likewise.
+ (vhsubq_x_n_u32): Likewise.
+ (vhsubq_x_s8): Likewise.
+ (vhsubq_x_s16): Likewise.
+ (vhsubq_x_s32): Likewise.
+ (vhsubq_x_u8): Likewise.
+ (vhsubq_x_u16): Likewise.
+ (vhsubq_x_u32): Likewise.
+ (vrhaddq_x_s8): Likewise.
+ (vrhaddq_x_s16): Likewise.
+ (vrhaddq_x_s32): Likewise.
+ (vrhaddq_x_u8): Likewise.
+ (vrhaddq_x_u16): Likewise.
+ (vrhaddq_x_u32): Likewise.
+ (vrmulhq_x_s8): Likewise.
+ (vrmulhq_x_s16): Likewise.
+ (vrmulhq_x_s32): Likewise.
+ (vrmulhq_x_u8): Likewise.
+ (vrmulhq_x_u16): Likewise.
+ (vrmulhq_x_u32): Likewise.
+ (vandq_x_s8): Likewise.
+ (vandq_x_s16): Likewise.
+ (vandq_x_s32): Likewise.
+ (vandq_x_u8): Likewise.
+ (vandq_x_u16): Likewise.
+ (vandq_x_u32): Likewise.
+ (vbicq_x_s8): Likewise.
+ (vbicq_x_s16): Likewise.
+ (vbicq_x_s32): Likewise.
+ (vbicq_x_u8): Likewise.
+ (vbicq_x_u16): Likewise.
+ (vbicq_x_u32): Likewise.
+ (vbrsrq_x_n_s8): Likewise.
+ (vbrsrq_x_n_s16): Likewise.
+ (vbrsrq_x_n_s32): Likewise.
+ (vbrsrq_x_n_u8): Likewise.
+ (vbrsrq_x_n_u16): Likewise.
+ (vbrsrq_x_n_u32): Likewise.
+ (veorq_x_s8): Likewise.
+ (veorq_x_s16): Likewise.
+ (veorq_x_s32): Likewise.
+ (veorq_x_u8): Likewise.
+ (veorq_x_u16): Likewise.
+ (veorq_x_u32): Likewise.
+ (vmovlbq_x_s8): Likewise.
+ (vmovlbq_x_s16): Likewise.
+ (vmovlbq_x_u8): Likewise.
+ (vmovlbq_x_u16): Likewise.
+ (vmovltq_x_s8): Likewise.
+ (vmovltq_x_s16): Likewise.
+ (vmovltq_x_u8): Likewise.
+ (vmovltq_x_u16): Likewise.
+ (vmvnq_x_s8): Likewise.
+ (vmvnq_x_s16): Likewise.
+ (vmvnq_x_s32): Likewise.
+ (vmvnq_x_u8): Likewise.
+ (vmvnq_x_u16): Likewise.
+ (vmvnq_x_u32): Likewise.
+ (vmvnq_x_n_s16): Likewise.
+ (vmvnq_x_n_s32): Likewise.
+ (vmvnq_x_n_u16): Likewise.
+ (vmvnq_x_n_u32): Likewise.
+ (vornq_x_s8): Likewise.
+ (vornq_x_s16): Likewise.
+ (vornq_x_s32): Likewise.
+ (vornq_x_u8): Likewise.
+ (vornq_x_u16): Likewise.
+ (vornq_x_u32): Likewise.
+ (vorrq_x_s8): Likewise.
+ (vorrq_x_s16): Likewise.
+ (vorrq_x_s32): Likewise.
+ (vorrq_x_u8): Likewise.
+ (vorrq_x_u16): Likewise.
+ (vorrq_x_u32): Likewise.
+ (vrev16q_x_s8): Likewise.
+ (vrev16q_x_u8): Likewise.
+ (vrev32q_x_s8): Likewise.
+ (vrev32q_x_s16): Likewise.
+ (vrev32q_x_u8): Likewise.
+ (vrev32q_x_u16): Likewise.
+ (vrev64q_x_s8): Likewise.
+ (vrev64q_x_s16): Likewise.
+ (vrev64q_x_s32): Likewise.
+ (vrev64q_x_u8): Likewise.
+ (vrev64q_x_u16): Likewise.
+ (vrev64q_x_u32): Likewise.
+ (vrshlq_x_s8): Likewise.
+ (vrshlq_x_s16): Likewise.
+ (vrshlq_x_s32): Likewise.
+ (vrshlq_x_u8): Likewise.
+ (vrshlq_x_u16): Likewise.
+ (vrshlq_x_u32): Likewise.
+ (vshllbq_x_n_s8): Likewise.
+ (vshllbq_x_n_s16): Likewise.
+ (vshllbq_x_n_u8): Likewise.
+ (vshllbq_x_n_u16): Likewise.
+ (vshlltq_x_n_s8): Likewise.
+ (vshlltq_x_n_s16): Likewise.
+ (vshlltq_x_n_u8): Likewise.
+ (vshlltq_x_n_u16): Likewise.
+ (vshlq_x_s8): Likewise.
+ (vshlq_x_s16): Likewise.
+ (vshlq_x_s32): Likewise.
+ (vshlq_x_u8): Likewise.
+ (vshlq_x_u16): Likewise.
+ (vshlq_x_u32): Likewise.
+ (vshlq_x_n_s8): Likewise.
+ (vshlq_x_n_s16): Likewise.
+ (vshlq_x_n_s32): Likewise.
+ (vshlq_x_n_u8): Likewise.
+ (vshlq_x_n_u16): Likewise.
+ (vshlq_x_n_u32): Likewise.
+ (vrshrq_x_n_s8): Likewise.
+ (vrshrq_x_n_s16): Likewise.
+ (vrshrq_x_n_s32): Likewise.
+ (vrshrq_x_n_u8): Likewise.
+ (vrshrq_x_n_u16): Likewise.
+ (vrshrq_x_n_u32): Likewise.
+ (vshrq_x_n_s8): Likewise.
+ (vshrq_x_n_s16): Likewise.
+ (vshrq_x_n_s32): Likewise.
+ (vshrq_x_n_u8): Likewise.
+ (vshrq_x_n_u16): Likewise.
+ (vshrq_x_n_u32): Likewise.
+ (vdupq_x_n_f16): Likewise.
+ (vdupq_x_n_f32): Likewise.
+ (vminnmq_x_f16): Likewise.
+ (vminnmq_x_f32): Likewise.
+ (vmaxnmq_x_f16): Likewise.
+ (vmaxnmq_x_f32): Likewise.
+ (vabdq_x_f16): Likewise.
+ (vabdq_x_f32): Likewise.
+ (vabsq_x_f16): Likewise.
+ (vabsq_x_f32): Likewise.
+ (vaddq_x_f16): Likewise.
+ (vaddq_x_f32): Likewise.
+ (vaddq_x_n_f16): Likewise.
+ (vaddq_x_n_f32): Likewise.
+ (vnegq_x_f16): Likewise.
+ (vnegq_x_f32): Likewise.
+ (vmulq_x_f16): Likewise.
+ (vmulq_x_f32): Likewise.
+ (vmulq_x_n_f16): Likewise.
+ (vmulq_x_n_f32): Likewise.
+ (vsubq_x_f16): Likewise.
+ (vsubq_x_f32): Likewise.
+ (vsubq_x_n_f16): Likewise.
+ (vsubq_x_n_f32): Likewise.
+ (vcaddq_rot90_x_f16): Likewise.
+ (vcaddq_rot90_x_f32): Likewise.
+ (vcaddq_rot270_x_f16): Likewise.
+ (vcaddq_rot270_x_f32): Likewise.
+ (vcmulq_x_f16): Likewise.
+ (vcmulq_x_f32): Likewise.
+ (vcmulq_rot90_x_f16): Likewise.
+ (vcmulq_rot90_x_f32): Likewise.
+ (vcmulq_rot180_x_f16): Likewise.
+ (vcmulq_rot180_x_f32): Likewise.
+ (vcmulq_rot270_x_f16): Likewise.
+ (vcmulq_rot270_x_f32): Likewise.
+ (vcvtaq_x_s16_f16): Likewise.
+ (vcvtaq_x_s32_f32): Likewise.
+ (vcvtaq_x_u16_f16): Likewise.
+ (vcvtaq_x_u32_f32): Likewise.
+ (vcvtnq_x_s16_f16): Likewise.
+ (vcvtnq_x_s32_f32): Likewise.
+ (vcvtnq_x_u16_f16): Likewise.
+ (vcvtnq_x_u32_f32): Likewise.
+ (vcvtpq_x_s16_f16): Likewise.
+ (vcvtpq_x_s32_f32): Likewise.
+ (vcvtpq_x_u16_f16): Likewise.
+ (vcvtpq_x_u32_f32): Likewise.
+ (vcvtmq_x_s16_f16): Likewise.
+ (vcvtmq_x_s32_f32): Likewise.
+ (vcvtmq_x_u16_f16): Likewise.
+ (vcvtmq_x_u32_f32): Likewise.
+ (vcvtbq_x_f32_f16): Likewise.
+ (vcvttq_x_f32_f16): Likewise.
+ (vcvtq_x_f16_u16): Likewise.
+ (vcvtq_x_f16_s16): Likewise.
+ (vcvtq_x_f32_s32): Likewise.
+ (vcvtq_x_f32_u32): Likewise.
+ (vcvtq_x_n_f16_s16): Likewise.
+ (vcvtq_x_n_f16_u16): Likewise.
+ (vcvtq_x_n_f32_s32): Likewise.
+ (vcvtq_x_n_f32_u32): Likewise.
+ (vcvtq_x_s16_f16): Likewise.
+ (vcvtq_x_s32_f32): Likewise.
+ (vcvtq_x_u16_f16): Likewise.
+ (vcvtq_x_u32_f32): Likewise.
+ (vcvtq_x_n_s16_f16): Likewise.
+ (vcvtq_x_n_s32_f32): Likewise.
+ (vcvtq_x_n_u16_f16): Likewise.
+ (vcvtq_x_n_u32_f32): Likewise.
+ (vrndq_x_f16): Likewise.
+ (vrndq_x_f32): Likewise.
+ (vrndnq_x_f16): Likewise.
+ (vrndnq_x_f32): Likewise.
+ (vrndmq_x_f16): Likewise.
+ (vrndmq_x_f32): Likewise.
+ (vrndpq_x_f16): Likewise.
+ (vrndpq_x_f32): Likewise.
+ (vrndaq_x_f16): Likewise.
+ (vrndaq_x_f32): Likewise.
+ (vrndxq_x_f16): Likewise.
+ (vrndxq_x_f32): Likewise.
+ (vandq_x_f16): Likewise.
+ (vandq_x_f32): Likewise.
+ (vbicq_x_f16): Likewise.
+ (vbicq_x_f32): Likewise.
+ (vbrsrq_x_n_f16): Likewise.
+ (vbrsrq_x_n_f32): Likewise.
+ (veorq_x_f16): Likewise.
+ (veorq_x_f32): Likewise.
+ (vornq_x_f16): Likewise.
+ (vornq_x_f32): Likewise.
+ (vorrq_x_f16): Likewise.
+ (vorrq_x_f32): Likewise.
+ (vrev32q_x_f16): Likewise.
+ (vrev64q_x_f16): Likewise.
+ (vrev64q_x_f32): Likewise.
+ (__arm_vddupq_x_n_u8): Define intrinsic.
+ (__arm_vddupq_x_n_u16): Likewise.
+ (__arm_vddupq_x_n_u32): Likewise.
+ (__arm_vddupq_x_wb_u8): Likewise.
+ (__arm_vddupq_x_wb_u16): Likewise.
+ (__arm_vddupq_x_wb_u32): Likewise.
+ (__arm_vdwdupq_x_n_u8): Likewise.
+ (__arm_vdwdupq_x_n_u16): Likewise.
+ (__arm_vdwdupq_x_n_u32): Likewise.
+ (__arm_vdwdupq_x_wb_u8): Likewise.
+ (__arm_vdwdupq_x_wb_u16): Likewise.
+ (__arm_vdwdupq_x_wb_u32): Likewise.
+ (__arm_vidupq_x_n_u8): Likewise.
+ (__arm_vidupq_x_n_u16): Likewise.
+ (__arm_vidupq_x_n_u32): Likewise.
+ (__arm_vidupq_x_wb_u8): Likewise.
+ (__arm_vidupq_x_wb_u16): Likewise.
+ (__arm_vidupq_x_wb_u32): Likewise.
+ (__arm_viwdupq_x_n_u8): Likewise.
+ (__arm_viwdupq_x_n_u16): Likewise.
+ (__arm_viwdupq_x_n_u32): Likewise.
+ (__arm_viwdupq_x_wb_u8): Likewise.
+ (__arm_viwdupq_x_wb_u16): Likewise.
+ (__arm_viwdupq_x_wb_u32): Likewise.
+ (__arm_vdupq_x_n_s8): Likewise.
+ (__arm_vdupq_x_n_s16): Likewise.
+ (__arm_vdupq_x_n_s32): Likewise.
+ (__arm_vdupq_x_n_u8): Likewise.
+ (__arm_vdupq_x_n_u16): Likewise.
+ (__arm_vdupq_x_n_u32): Likewise.
+ (__arm_vminq_x_s8): Likewise.
+ (__arm_vminq_x_s16): Likewise.
+ (__arm_vminq_x_s32): Likewise.
+ (__arm_vminq_x_u8): Likewise.
+ (__arm_vminq_x_u16): Likewise.
+ (__arm_vminq_x_u32): Likewise.
+ (__arm_vmaxq_x_s8): Likewise.
+ (__arm_vmaxq_x_s16): Likewise.
+ (__arm_vmaxq_x_s32): Likewise.
+ (__arm_vmaxq_x_u8): Likewise.
+ (__arm_vmaxq_x_u16): Likewise.
+ (__arm_vmaxq_x_u32): Likewise.
+ (__arm_vabdq_x_s8): Likewise.
+ (__arm_vabdq_x_s16): Likewise.
+ (__arm_vabdq_x_s32): Likewise.
+ (__arm_vabdq_x_u8): Likewise.
+ (__arm_vabdq_x_u16): Likewise.
+ (__arm_vabdq_x_u32): Likewise.
+ (__arm_vabsq_x_s8): Likewise.
+ (__arm_vabsq_x_s16): Likewise.
+ (__arm_vabsq_x_s32): Likewise.
+ (__arm_vaddq_x_s8): Likewise.
+ (__arm_vaddq_x_s16): Likewise.
+ (__arm_vaddq_x_s32): Likewise.
+ (__arm_vaddq_x_n_s8): Likewise.
+ (__arm_vaddq_x_n_s16): Likewise.
+ (__arm_vaddq_x_n_s32): Likewise.
+ (__arm_vaddq_x_u8): Likewise.
+ (__arm_vaddq_x_u16): Likewise.
+ (__arm_vaddq_x_u32): Likewise.
+ (__arm_vaddq_x_n_u8): Likewise.
+ (__arm_vaddq_x_n_u16): Likewise.
+ (__arm_vaddq_x_n_u32): Likewise.
+ (__arm_vclsq_x_s8): Likewise.
+ (__arm_vclsq_x_s16): Likewise.
+ (__arm_vclsq_x_s32): Likewise.
+ (__arm_vclzq_x_s8): Likewise.
+ (__arm_vclzq_x_s16): Likewise.
+ (__arm_vclzq_x_s32): Likewise.
+ (__arm_vclzq_x_u8): Likewise.
+ (__arm_vclzq_x_u16): Likewise.
+ (__arm_vclzq_x_u32): Likewise.
+ (__arm_vnegq_x_s8): Likewise.
+ (__arm_vnegq_x_s16): Likewise.
+ (__arm_vnegq_x_s32): Likewise.
+ (__arm_vmulhq_x_s8): Likewise.
+ (__arm_vmulhq_x_s16): Likewise.
+ (__arm_vmulhq_x_s32): Likewise.
+ (__arm_vmulhq_x_u8): Likewise.
+ (__arm_vmulhq_x_u16): Likewise.
+ (__arm_vmulhq_x_u32): Likewise.
+ (__arm_vmullbq_poly_x_p8): Likewise.
+ (__arm_vmullbq_poly_x_p16): Likewise.
+ (__arm_vmullbq_int_x_s8): Likewise.
+ (__arm_vmullbq_int_x_s16): Likewise.
+ (__arm_vmullbq_int_x_s32): Likewise.
+ (__arm_vmullbq_int_x_u8): Likewise.
+ (__arm_vmullbq_int_x_u16): Likewise.
+ (__arm_vmullbq_int_x_u32): Likewise.
+ (__arm_vmulltq_poly_x_p8): Likewise.
+ (__arm_vmulltq_poly_x_p16): Likewise.
+ (__arm_vmulltq_int_x_s8): Likewise.
+ (__arm_vmulltq_int_x_s16): Likewise.
+ (__arm_vmulltq_int_x_s32): Likewise.
+ (__arm_vmulltq_int_x_u8): Likewise.
+ (__arm_vmulltq_int_x_u16): Likewise.
+ (__arm_vmulltq_int_x_u32): Likewise.
+ (__arm_vmulq_x_s8): Likewise.
+ (__arm_vmulq_x_s16): Likewise.
+ (__arm_vmulq_x_s32): Likewise.
+ (__arm_vmulq_x_n_s8): Likewise.
+ (__arm_vmulq_x_n_s16): Likewise.
+ (__arm_vmulq_x_n_s32): Likewise.
+ (__arm_vmulq_x_u8): Likewise.
+ (__arm_vmulq_x_u16): Likewise.
+ (__arm_vmulq_x_u32): Likewise.
+ (__arm_vmulq_x_n_u8): Likewise.
+ (__arm_vmulq_x_n_u16): Likewise.
+ (__arm_vmulq_x_n_u32): Likewise.
+ (__arm_vsubq_x_s8): Likewise.
+ (__arm_vsubq_x_s16): Likewise.
+ (__arm_vsubq_x_s32): Likewise.
+ (__arm_vsubq_x_n_s8): Likewise.
+ (__arm_vsubq_x_n_s16): Likewise.
+ (__arm_vsubq_x_n_s32): Likewise.
+ (__arm_vsubq_x_u8): Likewise.
+ (__arm_vsubq_x_u16): Likewise.
+ (__arm_vsubq_x_u32): Likewise.
+ (__arm_vsubq_x_n_u8): Likewise.
+ (__arm_vsubq_x_n_u16): Likewise.
+ (__arm_vsubq_x_n_u32): Likewise.
+ (__arm_vcaddq_rot90_x_s8): Likewise.
+ (__arm_vcaddq_rot90_x_s16): Likewise.
+ (__arm_vcaddq_rot90_x_s32): Likewise.
+ (__arm_vcaddq_rot90_x_u8): Likewise.
+ (__arm_vcaddq_rot90_x_u16): Likewise.
+ (__arm_vcaddq_rot90_x_u32): Likewise.
+ (__arm_vcaddq_rot270_x_s8): Likewise.
+ (__arm_vcaddq_rot270_x_s16): Likewise.
+ (__arm_vcaddq_rot270_x_s32): Likewise.
+ (__arm_vcaddq_rot270_x_u8): Likewise.
+ (__arm_vcaddq_rot270_x_u16): Likewise.
+ (__arm_vcaddq_rot270_x_u32): Likewise.
+ (__arm_vhaddq_x_n_s8): Likewise.
+ (__arm_vhaddq_x_n_s16): Likewise.
+ (__arm_vhaddq_x_n_s32): Likewise.
+ (__arm_vhaddq_x_n_u8): Likewise.
+ (__arm_vhaddq_x_n_u16): Likewise.
+ (__arm_vhaddq_x_n_u32): Likewise.
+ (__arm_vhaddq_x_s8): Likewise.
+ (__arm_vhaddq_x_s16): Likewise.
+ (__arm_vhaddq_x_s32): Likewise.
+ (__arm_vhaddq_x_u8): Likewise.
+ (__arm_vhaddq_x_u16): Likewise.
+ (__arm_vhaddq_x_u32): Likewise.
+ (__arm_vhcaddq_rot90_x_s8): Likewise.
+ (__arm_vhcaddq_rot90_x_s16): Likewise.
+ (__arm_vhcaddq_rot90_x_s32): Likewise.
+ (__arm_vhcaddq_rot270_x_s8): Likewise.
+ (__arm_vhcaddq_rot270_x_s16): Likewise.
+ (__arm_vhcaddq_rot270_x_s32): Likewise.
+ (__arm_vhsubq_x_n_s8): Likewise.
+ (__arm_vhsubq_x_n_s16): Likewise.
+ (__arm_vhsubq_x_n_s32): Likewise.
+ (__arm_vhsubq_x_n_u8): Likewise.
+ (__arm_vhsubq_x_n_u16): Likewise.
+ (__arm_vhsubq_x_n_u32): Likewise.
+ (__arm_vhsubq_x_s8): Likewise.
+ (__arm_vhsubq_x_s16): Likewise.
+ (__arm_vhsubq_x_s32): Likewise.
+ (__arm_vhsubq_x_u8): Likewise.
+ (__arm_vhsubq_x_u16): Likewise.
+ (__arm_vhsubq_x_u32): Likewise.
+ (__arm_vrhaddq_x_s8): Likewise.
+ (__arm_vrhaddq_x_s16): Likewise.
+ (__arm_vrhaddq_x_s32): Likewise.
+ (__arm_vrhaddq_x_u8): Likewise.
+ (__arm_vrhaddq_x_u16): Likewise.
+ (__arm_vrhaddq_x_u32): Likewise.
+ (__arm_vrmulhq_x_s8): Likewise.
+ (__arm_vrmulhq_x_s16): Likewise.
+ (__arm_vrmulhq_x_s32): Likewise.
+ (__arm_vrmulhq_x_u8): Likewise.
+ (__arm_vrmulhq_x_u16): Likewise.
+ (__arm_vrmulhq_x_u32): Likewise.
+ (__arm_vandq_x_s8): Likewise.
+ (__arm_vandq_x_s16): Likewise.
+ (__arm_vandq_x_s32): Likewise.
+ (__arm_vandq_x_u8): Likewise.
+ (__arm_vandq_x_u16): Likewise.
+ (__arm_vandq_x_u32): Likewise.
+ (__arm_vbicq_x_s8): Likewise.
+ (__arm_vbicq_x_s16): Likewise.
+ (__arm_vbicq_x_s32): Likewise.
+ (__arm_vbicq_x_u8): Likewise.
+ (__arm_vbicq_x_u16): Likewise.
+ (__arm_vbicq_x_u32): Likewise.
+ (__arm_vbrsrq_x_n_s8): Likewise.
+ (__arm_vbrsrq_x_n_s16): Likewise.
+ (__arm_vbrsrq_x_n_s32): Likewise.
+ (__arm_vbrsrq_x_n_u8): Likewise.
+ (__arm_vbrsrq_x_n_u16): Likewise.
+ (__arm_vbrsrq_x_n_u32): Likewise.
+ (__arm_veorq_x_s8): Likewise.
+ (__arm_veorq_x_s16): Likewise.
+ (__arm_veorq_x_s32): Likewise.
+ (__arm_veorq_x_u8): Likewise.
+ (__arm_veorq_x_u16): Likewise.
+ (__arm_veorq_x_u32): Likewise.
+ (__arm_vmovlbq_x_s8): Likewise.
+ (__arm_vmovlbq_x_s16): Likewise.
+ (__arm_vmovlbq_x_u8): Likewise.
+ (__arm_vmovlbq_x_u16): Likewise.
+ (__arm_vmovltq_x_s8): Likewise.
+ (__arm_vmovltq_x_s16): Likewise.
+ (__arm_vmovltq_x_u8): Likewise.
+ (__arm_vmovltq_x_u16): Likewise.
+ (__arm_vmvnq_x_s8): Likewise.
+ (__arm_vmvnq_x_s16): Likewise.
+ (__arm_vmvnq_x_s32): Likewise.
+ (__arm_vmvnq_x_u8): Likewise.
+ (__arm_vmvnq_x_u16): Likewise.
+ (__arm_vmvnq_x_u32): Likewise.
+ (__arm_vmvnq_x_n_s16): Likewise.
+ (__arm_vmvnq_x_n_s32): Likewise.
+ (__arm_vmvnq_x_n_u16): Likewise.
+ (__arm_vmvnq_x_n_u32): Likewise.
+ (__arm_vornq_x_s8): Likewise.
+ (__arm_vornq_x_s16): Likewise.
+ (__arm_vornq_x_s32): Likewise.
+ (__arm_vornq_x_u8): Likewise.
+ (__arm_vornq_x_u16): Likewise.
+ (__arm_vornq_x_u32): Likewise.
+ (__arm_vorrq_x_s8): Likewise.
+ (__arm_vorrq_x_s16): Likewise.
+ (__arm_vorrq_x_s32): Likewise.
+ (__arm_vorrq_x_u8): Likewise.
+ (__arm_vorrq_x_u16): Likewise.
+ (__arm_vorrq_x_u32): Likewise.
+ (__arm_vrev16q_x_s8): Likewise.
+ (__arm_vrev16q_x_u8): Likewise.
+ (__arm_vrev32q_x_s8): Likewise.
+ (__arm_vrev32q_x_s16): Likewise.
+ (__arm_vrev32q_x_u8): Likewise.
+ (__arm_vrev32q_x_u16): Likewise.
+ (__arm_vrev64q_x_s8): Likewise.
+ (__arm_vrev64q_x_s16): Likewise.
+ (__arm_vrev64q_x_s32): Likewise.
+ (__arm_vrev64q_x_u8): Likewise.
+ (__arm_vrev64q_x_u16): Likewise.
+ (__arm_vrev64q_x_u32): Likewise.
+ (__arm_vrshlq_x_s8): Likewise.
+ (__arm_vrshlq_x_s16): Likewise.
+ (__arm_vrshlq_x_s32): Likewise.
+ (__arm_vrshlq_x_u8): Likewise.
+ (__arm_vrshlq_x_u16): Likewise.
+ (__arm_vrshlq_x_u32): Likewise.
+ (__arm_vshllbq_x_n_s8): Likewise.
+ (__arm_vshllbq_x_n_s16): Likewise.
+ (__arm_vshllbq_x_n_u8): Likewise.
+ (__arm_vshllbq_x_n_u16): Likewise.
+ (__arm_vshlltq_x_n_s8): Likewise.
+ (__arm_vshlltq_x_n_s16): Likewise.
+ (__arm_vshlltq_x_n_u8): Likewise.
+ (__arm_vshlltq_x_n_u16): Likewise.
+ (__arm_vshlq_x_s8): Likewise.
+ (__arm_vshlq_x_s16): Likewise.
+ (__arm_vshlq_x_s32): Likewise.
+ (__arm_vshlq_x_u8): Likewise.
+ (__arm_vshlq_x_u16): Likewise.
+ (__arm_vshlq_x_u32): Likewise.
+ (__arm_vshlq_x_n_s8): Likewise.
+ (__arm_vshlq_x_n_s16): Likewise.
+ (__arm_vshlq_x_n_s32): Likewise.
+ (__arm_vshlq_x_n_u8): Likewise.
+ (__arm_vshlq_x_n_u16): Likewise.
+ (__arm_vshlq_x_n_u32): Likewise.
+ (__arm_vrshrq_x_n_s8): Likewise.
+ (__arm_vrshrq_x_n_s16): Likewise.
+ (__arm_vrshrq_x_n_s32): Likewise.
+ (__arm_vrshrq_x_n_u8): Likewise.
+ (__arm_vrshrq_x_n_u16): Likewise.
+ (__arm_vrshrq_x_n_u32): Likewise.
+ (__arm_vshrq_x_n_s8): Likewise.
+ (__arm_vshrq_x_n_s16): Likewise.
+ (__arm_vshrq_x_n_s32): Likewise.
+ (__arm_vshrq_x_n_u8): Likewise.
+ (__arm_vshrq_x_n_u16): Likewise.
+ (__arm_vshrq_x_n_u32): Likewise.
+ (__arm_vdupq_x_n_f16): Likewise.
+ (__arm_vdupq_x_n_f32): Likewise.
+ (__arm_vminnmq_x_f16): Likewise.
+ (__arm_vminnmq_x_f32): Likewise.
+ (__arm_vmaxnmq_x_f16): Likewise.
+ (__arm_vmaxnmq_x_f32): Likewise.
+ (__arm_vabdq_x_f16): Likewise.
+ (__arm_vabdq_x_f32): Likewise.
+ (__arm_vabsq_x_f16): Likewise.
+ (__arm_vabsq_x_f32): Likewise.
+ (__arm_vaddq_x_f16): Likewise.
+ (__arm_vaddq_x_f32): Likewise.
+ (__arm_vaddq_x_n_f16): Likewise.
+ (__arm_vaddq_x_n_f32): Likewise.
+ (__arm_vnegq_x_f16): Likewise.
+ (__arm_vnegq_x_f32): Likewise.
+ (__arm_vmulq_x_f16): Likewise.
+ (__arm_vmulq_x_f32): Likewise.
+ (__arm_vmulq_x_n_f16): Likewise.
+ (__arm_vmulq_x_n_f32): Likewise.
+ (__arm_vsubq_x_f16): Likewise.
+ (__arm_vsubq_x_f32): Likewise.
+ (__arm_vsubq_x_n_f16): Likewise.
+ (__arm_vsubq_x_n_f32): Likewise.
+ (__arm_vcaddq_rot90_x_f16): Likewise.
+ (__arm_vcaddq_rot90_x_f32): Likewise.
+ (__arm_vcaddq_rot270_x_f16): Likewise.
+ (__arm_vcaddq_rot270_x_f32): Likewise.
+ (__arm_vcmulq_x_f16): Likewise.
+ (__arm_vcmulq_x_f32): Likewise.
+ (__arm_vcmulq_rot90_x_f16): Likewise.
+ (__arm_vcmulq_rot90_x_f32): Likewise.
+ (__arm_vcmulq_rot180_x_f16): Likewise.
+ (__arm_vcmulq_rot180_x_f32): Likewise.
+ (__arm_vcmulq_rot270_x_f16): Likewise.
+ (__arm_vcmulq_rot270_x_f32): Likewise.
+ (__arm_vcvtaq_x_s16_f16): Likewise.
+ (__arm_vcvtaq_x_s32_f32): Likewise.
+ (__arm_vcvtaq_x_u16_f16): Likewise.
+ (__arm_vcvtaq_x_u32_f32): Likewise.
+ (__arm_vcvtnq_x_s16_f16): Likewise.
+ (__arm_vcvtnq_x_s32_f32): Likewise.
+ (__arm_vcvtnq_x_u16_f16): Likewise.
+ (__arm_vcvtnq_x_u32_f32): Likewise.
+ (__arm_vcvtpq_x_s16_f16): Likewise.
+ (__arm_vcvtpq_x_s32_f32): Likewise.
+ (__arm_vcvtpq_x_u16_f16): Likewise.
+ (__arm_vcvtpq_x_u32_f32): Likewise.
+ (__arm_vcvtmq_x_s16_f16): Likewise.
+ (__arm_vcvtmq_x_s32_f32): Likewise.
+ (__arm_vcvtmq_x_u16_f16): Likewise.
+ (__arm_vcvtmq_x_u32_f32): Likewise.
+ (__arm_vcvtbq_x_f32_f16): Likewise.
+ (__arm_vcvttq_x_f32_f16): Likewise.
+ (__arm_vcvtq_x_f16_u16): Likewise.
+ (__arm_vcvtq_x_f16_s16): Likewise.
+ (__arm_vcvtq_x_f32_s32): Likewise.
+ (__arm_vcvtq_x_f32_u32): Likewise.
+ (__arm_vcvtq_x_n_f16_s16): Likewise.
+ (__arm_vcvtq_x_n_f16_u16): Likewise.
+ (__arm_vcvtq_x_n_f32_s32): Likewise.
+ (__arm_vcvtq_x_n_f32_u32): Likewise.
+ (__arm_vcvtq_x_s16_f16): Likewise.
+ (__arm_vcvtq_x_s32_f32): Likewise.
+ (__arm_vcvtq_x_u16_f16): Likewise.
+ (__arm_vcvtq_x_u32_f32): Likewise.
+ (__arm_vcvtq_x_n_s16_f16): Likewise.
+ (__arm_vcvtq_x_n_s32_f32): Likewise.
+ (__arm_vcvtq_x_n_u16_f16): Likewise.
+ (__arm_vcvtq_x_n_u32_f32): Likewise.
+ (__arm_vrndq_x_f16): Likewise.
+ (__arm_vrndq_x_f32): Likewise.
+ (__arm_vrndnq_x_f16): Likewise.
+ (__arm_vrndnq_x_f32): Likewise.
+ (__arm_vrndmq_x_f16): Likewise.
+ (__arm_vrndmq_x_f32): Likewise.
+ (__arm_vrndpq_x_f16): Likewise.
+ (__arm_vrndpq_x_f32): Likewise.
+ (__arm_vrndaq_x_f16): Likewise.
+ (__arm_vrndaq_x_f32): Likewise.
+ (__arm_vrndxq_x_f16): Likewise.
+ (__arm_vrndxq_x_f32): Likewise.
+ (__arm_vandq_x_f16): Likewise.
+ (__arm_vandq_x_f32): Likewise.
+ (__arm_vbicq_x_f16): Likewise.
+ (__arm_vbicq_x_f32): Likewise.
+ (__arm_vbrsrq_x_n_f16): Likewise.
+ (__arm_vbrsrq_x_n_f32): Likewise.
+ (__arm_veorq_x_f16): Likewise.
+ (__arm_veorq_x_f32): Likewise.
+ (__arm_vornq_x_f16): Likewise.
+ (__arm_vornq_x_f32): Likewise.
+ (__arm_vorrq_x_f16): Likewise.
+ (__arm_vorrq_x_f32): Likewise.
+ (__arm_vrev32q_x_f16): Likewise.
+ (__arm_vrev64q_x_f16): Likewise.
+ (__arm_vrev64q_x_f32): Likewise.
+ (vabdq_x): Define polymorphic variant.
+ (vabsq_x): Likewise.
+ (vaddq_x): Likewise.
+ (vandq_x): Likewise.
+ (vbicq_x): Likewise.
+ (vbrsrq_x): Likewise.
+ (vcaddq_rot270_x): Likewise.
+ (vcaddq_rot90_x): Likewise.
+ (vcmulq_rot180_x): Likewise.
+ (vcmulq_rot270_x): Likewise.
+ (vcmulq_x): Likewise.
+ (vcvtq_x): Likewise.
+ (vcvtq_x_n): Likewise.
+ (vcvtnq_m): Likewise.
+ (veorq_x): Likewise.
+ (vmaxnmq_x): Likewise.
+ (vminnmq_x): Likewise.
+ (vmulq_x): Likewise.
+ (vnegq_x): Likewise.
+ (vornq_x): Likewise.
+ (vorrq_x): Likewise.
+ (vrev32q_x): Likewise.
+ (vrev64q_x): Likewise.
+ (vrndaq_x): Likewise.
+ (vrndmq_x): Likewise.
+ (vrndnq_x): Likewise.
+ (vrndpq_x): Likewise.
+ (vrndq_x): Likewise.
+ (vrndxq_x): Likewise.
+ (vsubq_x): Likewise.
+ (vcmulq_rot90_x): Likewise.
+ (vadciq): Likewise.
+ (vclsq_x): Likewise.
+ (vclzq_x): Likewise.
+ (vhaddq_x): Likewise.
+ (vhcaddq_rot270_x): Likewise.
+ (vhcaddq_rot90_x): Likewise.
+ (vhsubq_x): Likewise.
+ (vmaxq_x): Likewise.
+ (vminq_x): Likewise.
+ (vmovlbq_x): Likewise.
+ (vmovltq_x): Likewise.
+ (vmulhq_x): Likewise.
+ (vmullbq_int_x): Likewise.
+ (vmullbq_poly_x): Likewise.
+ (vmulltq_int_x): Likewise.
+ (vmulltq_poly_x): Likewise.
+ (vmvnq_x): Likewise.
+ (vrev16q_x): Likewise.
+ (vrhaddq_x): Likewise.
+ (vrmulhq_x): Likewise.
+ (vrshlq_x): Likewise.
+ (vrshrq_x): Likewise.
+ (vshllbq_x): Likewise.
+ (vshlltq_x): Likewise.
+ (vshlq_x_n): Likewise.
+ (vshlq_x): Likewise.
+ (vdwdupq_x_u8): Likewise.
+ (vdwdupq_x_u16): Likewise.
+ (vdwdupq_x_u32): Likewise.
+ (viwdupq_x_u8): Likewise.
+ (viwdupq_x_u16): Likewise.
+ (viwdupq_x_u32): Likewise.
+ (vidupq_x_u8): Likewise.
+ (vddupq_x_u8): Likewise.
+ (vidupq_x_u16): Likewise.
+ (vddupq_x_u16): Likewise.
+ (vidupq_x_u32): Likewise.
+ (vddupq_x_u32): Likewise.
+ (vshrq_x): Likewise.
+
2020-03-20 Richard Biener <rguenther@suse.de>
* tree-vect-slp.c (vect_analyze_slp_instance): Push the stmts
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 969908b60f3..77df7c75c3f 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -2074,6 +2074,382 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
#define vstrwq_scatter_base_wb_s32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_s32(__addr, __offset, __value)
#define vstrwq_scatter_base_wb_u32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_u32(__addr, __offset, __value)
#define vstrwq_scatter_base_wb_f32(__addr, __offset, __value) __arm_vstrwq_scatter_base_wb_f32(__addr, __offset, __value)
+#define vddupq_x_n_u8(__a, __imm, __p) __arm_vddupq_x_n_u8(__a, __imm, __p)
+#define vddupq_x_n_u16(__a, __imm, __p) __arm_vddupq_x_n_u16(__a, __imm, __p)
+#define vddupq_x_n_u32(__a, __imm, __p) __arm_vddupq_x_n_u32(__a, __imm, __p)
+#define vddupq_x_wb_u8(__a, __imm, __p) __arm_vddupq_x_wb_u8(__a, __imm, __p)
+#define vddupq_x_wb_u16(__a, __imm, __p) __arm_vddupq_x_wb_u16(__a, __imm, __p)
+#define vddupq_x_wb_u32(__a, __imm, __p) __arm_vddupq_x_wb_u32(__a, __imm, __p)
+#define vdwdupq_x_n_u8(__a, __b, __imm, __p) __arm_vdwdupq_x_n_u8(__a, __b, __imm, __p)
+#define vdwdupq_x_n_u16(__a, __b, __imm, __p) __arm_vdwdupq_x_n_u16(__a, __b, __imm, __p)
+#define vdwdupq_x_n_u32(__a, __b, __imm, __p) __arm_vdwdupq_x_n_u32(__a, __b, __imm, __p)
+#define vdwdupq_x_wb_u8(__a, __b, __imm, __p) __arm_vdwdupq_x_wb_u8(__a, __b, __imm, __p)
+#define vdwdupq_x_wb_u16(__a, __b, __imm, __p) __arm_vdwdupq_x_wb_u16(__a, __b, __imm, __p)
+#define vdwdupq_x_wb_u32(__a, __b, __imm, __p) __arm_vdwdupq_x_wb_u32(__a, __b, __imm, __p)
+#define vidupq_x_n_u8(__a, __imm, __p) __arm_vidupq_x_n_u8(__a, __imm, __p)
+#define vidupq_x_n_u16(__a, __imm, __p) __arm_vidupq_x_n_u16(__a, __imm, __p)
+#define vidupq_x_n_u32(__a, __imm, __p) __arm_vidupq_x_n_u32(__a, __imm, __p)
+#define vidupq_x_wb_u8(__a, __imm, __p) __arm_vidupq_x_wb_u8(__a, __imm, __p)
+#define vidupq_x_wb_u16(__a, __imm, __p) __arm_vidupq_x_wb_u16(__a, __imm, __p)
+#define vidupq_x_wb_u32(__a, __imm, __p) __arm_vidupq_x_wb_u32(__a, __imm, __p)
+#define viwdupq_x_n_u8(__a, __b, __imm, __p) __arm_viwdupq_x_n_u8(__a, __b, __imm, __p)
+#define viwdupq_x_n_u16(__a, __b, __imm, __p) __arm_viwdupq_x_n_u16(__a, __b, __imm, __p)
+#define viwdupq_x_n_u32(__a, __b, __imm, __p) __arm_viwdupq_x_n_u32(__a, __b, __imm, __p)
+#define viwdupq_x_wb_u8(__a, __b, __imm, __p) __arm_viwdupq_x_wb_u8(__a, __b, __imm, __p)
+#define viwdupq_x_wb_u16(__a, __b, __imm, __p) __arm_viwdupq_x_wb_u16(__a, __b, __imm, __p)
+#define viwdupq_x_wb_u32(__a, __b, __imm, __p) __arm_viwdupq_x_wb_u32(__a, __b, __imm, __p)
+#define vdupq_x_n_s8(__a, __p) __arm_vdupq_x_n_s8(__a, __p)
+#define vdupq_x_n_s16(__a, __p) __arm_vdupq_x_n_s16(__a, __p)
+#define vdupq_x_n_s32(__a, __p) __arm_vdupq_x_n_s32(__a, __p)
+#define vdupq_x_n_u8(__a, __p) __arm_vdupq_x_n_u8(__a, __p)
+#define vdupq_x_n_u16(__a, __p) __arm_vdupq_x_n_u16(__a, __p)
+#define vdupq_x_n_u32(__a, __p) __arm_vdupq_x_n_u32(__a, __p)
+#define vminq_x_s8(__a, __b, __p) __arm_vminq_x_s8(__a, __b, __p)
+#define vminq_x_s16(__a, __b, __p) __arm_vminq_x_s16(__a, __b, __p)
+#define vminq_x_s32(__a, __b, __p) __arm_vminq_x_s32(__a, __b, __p)
+#define vminq_x_u8(__a, __b, __p) __arm_vminq_x_u8(__a, __b, __p)
+#define vminq_x_u16(__a, __b, __p) __arm_vminq_x_u16(__a, __b, __p)
+#define vminq_x_u32(__a, __b, __p) __arm_vminq_x_u32(__a, __b, __p)
+#define vmaxq_x_s8(__a, __b, __p) __arm_vmaxq_x_s8(__a, __b, __p)
+#define vmaxq_x_s16(__a, __b, __p) __arm_vmaxq_x_s16(__a, __b, __p)
+#define vmaxq_x_s32(__a, __b, __p) __arm_vmaxq_x_s32(__a, __b, __p)
+#define vmaxq_x_u8(__a, __b, __p) __arm_vmaxq_x_u8(__a, __b, __p)
+#define vmaxq_x_u16(__a, __b, __p) __arm_vmaxq_x_u16(__a, __b, __p)
+#define vmaxq_x_u32(__a, __b, __p) __arm_vmaxq_x_u32(__a, __b, __p)
+#define vabdq_x_s8(__a, __b, __p) __arm_vabdq_x_s8(__a, __b, __p)
+#define vabdq_x_s16(__a, __b, __p) __arm_vabdq_x_s16(__a, __b, __p)
+#define vabdq_x_s32(__a, __b, __p) __arm_vabdq_x_s32(__a, __b, __p)
+#define vabdq_x_u8(__a, __b, __p) __arm_vabdq_x_u8(__a, __b, __p)
+#define vabdq_x_u16(__a, __b, __p) __arm_vabdq_x_u16(__a, __b, __p)
+#define vabdq_x_u32(__a, __b, __p) __arm_vabdq_x_u32(__a, __b, __p)
+#define vabsq_x_s8(__a, __p) __arm_vabsq_x_s8(__a, __p)
+#define vabsq_x_s16(__a, __p) __arm_vabsq_x_s16(__a, __p)
+#define vabsq_x_s32(__a, __p) __arm_vabsq_x_s32(__a, __p)
+#define vaddq_x_s8(__a, __b, __p) __arm_vaddq_x_s8(__a, __b, __p)
+#define vaddq_x_s16(__a, __b, __p) __arm_vaddq_x_s16(__a, __b, __p)
+#define vaddq_x_s32(__a, __b, __p) __arm_vaddq_x_s32(__a, __b, __p)
+#define vaddq_x_n_s8(__a, __b, __p) __arm_vaddq_x_n_s8(__a, __b, __p)
+#define vaddq_x_n_s16(__a, __b, __p) __arm_vaddq_x_n_s16(__a, __b, __p)
+#define vaddq_x_n_s32(__a, __b, __p) __arm_vaddq_x_n_s32(__a, __b, __p)
+#define vaddq_x_u8(__a, __b, __p) __arm_vaddq_x_u8(__a, __b, __p)
+#define vaddq_x_u16(__a, __b, __p) __arm_vaddq_x_u16(__a, __b, __p)
+#define vaddq_x_u32(__a, __b, __p) __arm_vaddq_x_u32(__a, __b, __p)
+#define vaddq_x_n_u8(__a, __b, __p) __arm_vaddq_x_n_u8(__a, __b, __p)
+#define vaddq_x_n_u16(__a, __b, __p) __arm_vaddq_x_n_u16(__a, __b, __p)
+#define vaddq_x_n_u32(__a, __b, __p) __arm_vaddq_x_n_u32(__a, __b, __p)
+#define vclsq_x_s8(__a, __p) __arm_vclsq_x_s8(__a, __p)
+#define vclsq_x_s16(__a, __p) __arm_vclsq_x_s16(__a, __p)
+#define vclsq_x_s32(__a, __p) __arm_vclsq_x_s32(__a, __p)
+#define vclzq_x_s8(__a, __p) __arm_vclzq_x_s8(__a, __p)
+#define vclzq_x_s16(__a, __p) __arm_vclzq_x_s16(__a, __p)
+#define vclzq_x_s32(__a, __p) __arm_vclzq_x_s32(__a, __p)
+#define vclzq_x_u8(__a, __p) __arm_vclzq_x_u8(__a, __p)
+#define vclzq_x_u16(__a, __p) __arm_vclzq_x_u16(__a, __p)
+#define vclzq_x_u32(__a, __p) __arm_vclzq_x_u32(__a, __p)
+#define vnegq_x_s8(__a, __p) __arm_vnegq_x_s8(__a, __p)
+#define vnegq_x_s16(__a, __p) __arm_vnegq_x_s16(__a, __p)
+#define vnegq_x_s32(__a, __p) __arm_vnegq_x_s32(__a, __p)
+#define vmulhq_x_s8(__a, __b, __p) __arm_vmulhq_x_s8(__a, __b, __p)
+#define vmulhq_x_s16(__a, __b, __p) __arm_vmulhq_x_s16(__a, __b, __p)
+#define vmulhq_x_s32(__a, __b, __p) __arm_vmulhq_x_s32(__a, __b, __p)
+#define vmulhq_x_u8(__a, __b, __p) __arm_vmulhq_x_u8(__a, __b, __p)
+#define vmulhq_x_u16(__a, __b, __p) __arm_vmulhq_x_u16(__a, __b, __p)
+#define vmulhq_x_u32(__a, __b, __p) __arm_vmulhq_x_u32(__a, __b, __p)
+#define vmullbq_poly_x_p8(__a, __b, __p) __arm_vmullbq_poly_x_p8(__a, __b, __p)
+#define vmullbq_poly_x_p16(__a, __b, __p) __arm_vmullbq_poly_x_p16(__a, __b, __p)
+#define vmullbq_int_x_s8(__a, __b, __p) __arm_vmullbq_int_x_s8(__a, __b, __p)
+#define vmullbq_int_x_s16(__a, __b, __p) __arm_vmullbq_int_x_s16(__a, __b, __p)
+#define vmullbq_int_x_s32(__a, __b, __p) __arm_vmullbq_int_x_s32(__a, __b, __p)
+#define vmullbq_int_x_u8(__a, __b, __p) __arm_vmullbq_int_x_u8(__a, __b, __p)
+#define vmullbq_int_x_u16(__a, __b, __p) __arm_vmullbq_int_x_u16(__a, __b, __p)
+#define vmullbq_int_x_u32(__a, __b, __p) __arm_vmullbq_int_x_u32(__a, __b, __p)
+#define vmulltq_poly_x_p8(__a, __b, __p) __arm_vmulltq_poly_x_p8(__a, __b, __p)
+#define vmulltq_poly_x_p16(__a, __b, __p) __arm_vmulltq_poly_x_p16(__a, __b, __p)
+#define vmulltq_int_x_s8(__a, __b, __p) __arm_vmulltq_int_x_s8(__a, __b, __p)
+#define vmulltq_int_x_s16(__a, __b, __p) __arm_vmulltq_int_x_s16(__a, __b, __p)
+#define vmulltq_int_x_s32(__a, __b, __p) __arm_vmulltq_int_x_s32(__a, __b, __p)
+#define vmulltq_int_x_u8(__a, __b, __p) __arm_vmulltq_int_x_u8(__a, __b, __p)
+#define vmulltq_int_x_u16(__a, __b, __p) __arm_vmulltq_int_x_u16(__a, __b, __p)
+#define vmulltq_int_x_u32(__a, __b, __p) __arm_vmulltq_int_x_u32(__a, __b, __p)
+#define vmulq_x_s8(__a, __b, __p) __arm_vmulq_x_s8(__a, __b, __p)
+#define vmulq_x_s16(__a, __b, __p) __arm_vmulq_x_s16(__a, __b, __p)
+#define vmulq_x_s32(__a, __b, __p) __arm_vmulq_x_s32(__a, __b, __p)
+#define vmulq_x_n_s8(__a, __b, __p) __arm_vmulq_x_n_s8(__a, __b, __p)
+#define vmulq_x_n_s16(__a, __b, __p) __arm_vmulq_x_n_s16(__a, __b, __p)
+#define vmulq_x_n_s32(__a, __b, __p) __arm_vmulq_x_n_s32(__a, __b, __p)
+#define vmulq_x_u8(__a, __b, __p) __arm_vmulq_x_u8(__a, __b, __p)
+#define vmulq_x_u16(__a, __b, __p) __arm_vmulq_x_u16(__a, __b, __p)
+#define vmulq_x_u32(__a, __b, __p) __arm_vmulq_x_u32(__a, __b, __p)
+#define vmulq_x_n_u8(__a, __b, __p) __arm_vmulq_x_n_u8(__a, __b, __p)
+#define vmulq_x_n_u16(__a, __b, __p) __arm_vmulq_x_n_u16(__a, __b, __p)
+#define vmulq_x_n_u32(__a, __b, __p) __arm_vmulq_x_n_u32(__a, __b, __p)
+#define vsubq_x_s8(__a, __b, __p) __arm_vsubq_x_s8(__a, __b, __p)
+#define vsubq_x_s16(__a, __b, __p) __arm_vsubq_x_s16(__a, __b, __p)
+#define vsubq_x_s32(__a, __b, __p) __arm_vsubq_x_s32(__a, __b, __p)
+#define vsubq_x_n_s8(__a, __b, __p) __arm_vsubq_x_n_s8(__a, __b, __p)
+#define vsubq_x_n_s16(__a, __b, __p) __arm_vsubq_x_n_s16(__a, __b, __p)
+#define vsubq_x_n_s32(__a, __b, __p) __arm_vsubq_x_n_s32(__a, __b, __p)
+#define vsubq_x_u8(__a, __b, __p) __arm_vsubq_x_u8(__a, __b, __p)
+#define vsubq_x_u16(__a, __b, __p) __arm_vsubq_x_u16(__a, __b, __p)
+#define vsubq_x_u32(__a, __b, __p) __arm_vsubq_x_u32(__a, __b, __p)
+#define vsubq_x_n_u8(__a, __b, __p) __arm_vsubq_x_n_u8(__a, __b, __p)
+#define vsubq_x_n_u16(__a, __b, __p) __arm_vsubq_x_n_u16(__a, __b, __p)
+#define vsubq_x_n_u32(__a, __b, __p) __arm_vsubq_x_n_u32(__a, __b, __p)
+#define vcaddq_rot90_x_s8(__a, __b, __p) __arm_vcaddq_rot90_x_s8(__a, __b, __p)
+#define vcaddq_rot90_x_s16(__a, __b, __p) __arm_vcaddq_rot90_x_s16(__a, __b, __p)
+#define vcaddq_rot90_x_s32(__a, __b, __p) __arm_vcaddq_rot90_x_s32(__a, __b, __p)
+#define vcaddq_rot90_x_u8(__a, __b, __p) __arm_vcaddq_rot90_x_u8(__a, __b, __p)
+#define vcaddq_rot90_x_u16(__a, __b, __p) __arm_vcaddq_rot90_x_u16(__a, __b, __p)
+#define vcaddq_rot90_x_u32(__a, __b, __p) __arm_vcaddq_rot90_x_u32(__a, __b, __p)
+#define vcaddq_rot270_x_s8(__a, __b, __p) __arm_vcaddq_rot270_x_s8(__a, __b, __p)
+#define vcaddq_rot270_x_s16(__a, __b, __p) __arm_vcaddq_rot270_x_s16(__a, __b, __p)
+#define vcaddq_rot270_x_s32(__a, __b, __p) __arm_vcaddq_rot270_x_s32(__a, __b, __p)
+#define vcaddq_rot270_x_u8(__a, __b, __p) __arm_vcaddq_rot270_x_u8(__a, __b, __p)
+#define vcaddq_rot270_x_u16(__a, __b, __p) __arm_vcaddq_rot270_x_u16(__a, __b, __p)
+#define vcaddq_rot270_x_u32(__a, __b, __p) __arm_vcaddq_rot270_x_u32(__a, __b, __p)
+#define vhaddq_x_n_s8(__a, __b, __p) __arm_vhaddq_x_n_s8(__a, __b, __p)
+#define vhaddq_x_n_s16(__a, __b, __p) __arm_vhaddq_x_n_s16(__a, __b, __p)
+#define vhaddq_x_n_s32(__a, __b, __p) __arm_vhaddq_x_n_s32(__a, __b, __p)
+#define vhaddq_x_n_u8(__a, __b, __p) __arm_vhaddq_x_n_u8(__a, __b, __p)
+#define vhaddq_x_n_u16(__a, __b, __p) __arm_vhaddq_x_n_u16(__a, __b, __p)
+#define vhaddq_x_n_u32(__a, __b, __p) __arm_vhaddq_x_n_u32(__a, __b, __p)
+#define vhaddq_x_s8(__a, __b, __p) __arm_vhaddq_x_s8(__a, __b, __p)
+#define vhaddq_x_s16(__a, __b, __p) __arm_vhaddq_x_s16(__a, __b, __p)
+#define vhaddq_x_s32(__a, __b, __p) __arm_vhaddq_x_s32(__a, __b, __p)
+#define vhaddq_x_u8(__a, __b, __p) __arm_vhaddq_x_u8(__a, __b, __p)
+#define vhaddq_x_u16(__a, __b, __p) __arm_vhaddq_x_u16(__a, __b, __p)
+#define vhaddq_x_u32(__a, __b, __p) __arm_vhaddq_x_u32(__a, __b, __p)
+#define vhcaddq_rot90_x_s8(__a, __b, __p) __arm_vhcaddq_rot90_x_s8(__a, __b, __p)
+#define vhcaddq_rot90_x_s16(__a, __b, __p) __arm_vhcaddq_rot90_x_s16(__a, __b, __p)
+#define vhcaddq_rot90_x_s32(__a, __b, __p) __arm_vhcaddq_rot90_x_s32(__a, __b, __p)
+#define vhcaddq_rot270_x_s8(__a, __b, __p) __arm_vhcaddq_rot270_x_s8(__a, __b, __p)
+#define vhcaddq_rot270_x_s16(__a, __b, __p) __arm_vhcaddq_rot270_x_s16(__a, __b, __p)
+#define vhcaddq_rot270_x_s32(__a, __b, __p) __arm_vhcaddq_rot270_x_s32(__a, __b, __p)
+#define vhsubq_x_n_s8(__a, __b, __p) __arm_vhsubq_x_n_s8(__a, __b, __p)
+#define vhsubq_x_n_s16(__a, __b, __p) __arm_vhsubq_x_n_s16(__a, __b, __p)
+#define vhsubq_x_n_s32(__a, __b, __p) __arm_vhsubq_x_n_s32(__a, __b, __p)
+#define vhsubq_x_n_u8(__a, __b, __p) __arm_vhsubq_x_n_u8(__a, __b, __p)
+#define vhsubq_x_n_u16(__a, __b, __p) __arm_vhsubq_x_n_u16(__a, __b, __p)
+#define vhsubq_x_n_u32(__a, __b, __p) __arm_vhsubq_x_n_u32(__a, __b, __p)
+#define vhsubq_x_s8(__a, __b, __p) __arm_vhsubq_x_s8(__a, __b, __p)
+#define vhsubq_x_s16(__a, __b, __p) __arm_vhsubq_x_s16(__a, __b, __p)
+#define vhsubq_x_s32(__a, __b, __p) __arm_vhsubq_x_s32(__a, __b, __p)
+#define vhsubq_x_u8(__a, __b, __p) __arm_vhsubq_x_u8(__a, __b, __p)
+#define vhsubq_x_u16(__a, __b, __p) __arm_vhsubq_x_u16(__a, __b, __p)
+#define vhsubq_x_u32(__a, __b, __p) __arm_vhsubq_x_u32(__a, __b, __p)
+#define vrhaddq_x_s8(__a, __b, __p) __arm_vrhaddq_x_s8(__a, __b, __p)
+#define vrhaddq_x_s16(__a, __b, __p) __arm_vrhaddq_x_s16(__a, __b, __p)
+#define vrhaddq_x_s32(__a, __b, __p) __arm_vrhaddq_x_s32(__a, __b, __p)
+#define vrhaddq_x_u8(__a, __b, __p) __arm_vrhaddq_x_u8(__a, __b, __p)
+#define vrhaddq_x_u16(__a, __b, __p) __arm_vrhaddq_x_u16(__a, __b, __p)
+#define vrhaddq_x_u32(__a, __b, __p) __arm_vrhaddq_x_u32(__a, __b, __p)
+#define vrmulhq_x_s8(__a, __b, __p) __arm_vrmulhq_x_s8(__a, __b, __p)
+#define vrmulhq_x_s16(__a, __b, __p) __arm_vrmulhq_x_s16(__a, __b, __p)
+#define vrmulhq_x_s32(__a, __b, __p) __arm_vrmulhq_x_s32(__a, __b, __p)
+#define vrmulhq_x_u8(__a, __b, __p) __arm_vrmulhq_x_u8(__a, __b, __p)
+#define vrmulhq_x_u16(__a, __b, __p) __arm_vrmulhq_x_u16(__a, __b, __p)
+#define vrmulhq_x_u32(__a, __b, __p) __arm_vrmulhq_x_u32(__a, __b, __p)
+#define vandq_x_s8(__a, __b, __p) __arm_vandq_x_s8(__a, __b, __p)
+#define vandq_x_s16(__a, __b, __p) __arm_vandq_x_s16(__a, __b, __p)
+#define vandq_x_s32(__a, __b, __p) __arm_vandq_x_s32(__a, __b, __p)
+#define vandq_x_u8(__a, __b, __p) __arm_vandq_x_u8(__a, __b, __p)
+#define vandq_x_u16(__a, __b, __p) __arm_vandq_x_u16(__a, __b, __p)
+#define vandq_x_u32(__a, __b, __p) __arm_vandq_x_u32(__a, __b, __p)
+#define vbicq_x_s8(__a, __b, __p) __arm_vbicq_x_s8(__a, __b, __p)
+#define vbicq_x_s16(__a, __b, __p) __arm_vbicq_x_s16(__a, __b, __p)
+#define vbicq_x_s32(__a, __b, __p) __arm_vbicq_x_s32(__a, __b, __p)
+#define vbicq_x_u8(__a, __b, __p) __arm_vbicq_x_u8(__a, __b, __p)
+#define vbicq_x_u16(__a, __b, __p) __arm_vbicq_x_u16(__a, __b, __p)
+#define vbicq_x_u32(__a, __b, __p) __arm_vbicq_x_u32(__a, __b, __p)
+#define vbrsrq_x_n_s8(__a, __b, __p) __arm_vbrsrq_x_n_s8(__a, __b, __p)
+#define vbrsrq_x_n_s16(__a, __b, __p) __arm_vbrsrq_x_n_s16(__a, __b, __p)
+#define vbrsrq_x_n_s32(__a, __b, __p) __arm_vbrsrq_x_n_s32(__a, __b, __p)
+#define vbrsrq_x_n_u8(__a, __b, __p) __arm_vbrsrq_x_n_u8(__a, __b, __p)
+#define vbrsrq_x_n_u16(__a, __b, __p) __arm_vbrsrq_x_n_u16(__a, __b, __p)
+#define vbrsrq_x_n_u32(__a, __b, __p) __arm_vbrsrq_x_n_u32(__a, __b, __p)
+#define veorq_x_s8(__a, __b, __p) __arm_veorq_x_s8(__a, __b, __p)
+#define veorq_x_s16(__a, __b, __p) __arm_veorq_x_s16(__a, __b, __p)
+#define veorq_x_s32(__a, __b, __p) __arm_veorq_x_s32(__a, __b, __p)
+#define veorq_x_u8(__a, __b, __p) __arm_veorq_x_u8(__a, __b, __p)
+#define veorq_x_u16(__a, __b, __p) __arm_veorq_x_u16(__a, __b, __p)
+#define veorq_x_u32(__a, __b, __p) __arm_veorq_x_u32(__a, __b, __p)
+#define vmovlbq_x_s8(__a, __p) __arm_vmovlbq_x_s8(__a, __p)
+#define vmovlbq_x_s16(__a, __p) __arm_vmovlbq_x_s16(__a, __p)
+#define vmovlbq_x_u8(__a, __p) __arm_vmovlbq_x_u8(__a, __p)
+#define vmovlbq_x_u16(__a, __p) __arm_vmovlbq_x_u16(__a, __p)
+#define vmovltq_x_s8(__a, __p) __arm_vmovltq_x_s8(__a, __p)
+#define vmovltq_x_s16(__a, __p) __arm_vmovltq_x_s16(__a, __p)
+#define vmovltq_x_u8(__a, __p) __arm_vmovltq_x_u8(__a, __p)
+#define vmovltq_x_u16(__a, __p) __arm_vmovltq_x_u16(__a, __p)
+#define vmvnq_x_s8(__a, __p) __arm_vmvnq_x_s8(__a, __p)
+#define vmvnq_x_s16(__a, __p) __arm_vmvnq_x_s16(__a, __p)
+#define vmvnq_x_s32(__a, __p) __arm_vmvnq_x_s32(__a, __p)
+#define vmvnq_x_u8(__a, __p) __arm_vmvnq_x_u8(__a, __p)
+#define vmvnq_x_u16(__a, __p) __arm_vmvnq_x_u16(__a, __p)
+#define vmvnq_x_u32(__a, __p) __arm_vmvnq_x_u32(__a, __p)
+#define vmvnq_x_n_s16( __imm, __p) __arm_vmvnq_x_n_s16( __imm, __p)
+#define vmvnq_x_n_s32( __imm, __p) __arm_vmvnq_x_n_s32( __imm, __p)
+#define vmvnq_x_n_u16( __imm, __p) __arm_vmvnq_x_n_u16( __imm, __p)
+#define vmvnq_x_n_u32( __imm, __p) __arm_vmvnq_x_n_u32( __imm, __p)
+#define vornq_x_s8(__a, __b, __p) __arm_vornq_x_s8(__a, __b, __p)
+#define vornq_x_s16(__a, __b, __p) __arm_vornq_x_s16(__a, __b, __p)
+#define vornq_x_s32(__a, __b, __p) __arm_vornq_x_s32(__a, __b, __p)
+#define vornq_x_u8(__a, __b, __p) __arm_vornq_x_u8(__a, __b, __p)
+#define vornq_x_u16(__a, __b, __p) __arm_vornq_x_u16(__a, __b, __p)
+#define vornq_x_u32(__a, __b, __p) __arm_vornq_x_u32(__a, __b, __p)
+#define vorrq_x_s8(__a, __b, __p) __arm_vorrq_x_s8(__a, __b, __p)
+#define vorrq_x_s16(__a, __b, __p) __arm_vorrq_x_s16(__a, __b, __p)
+#define vorrq_x_s32(__a, __b, __p) __arm_vorrq_x_s32(__a, __b, __p)
+#define vorrq_x_u8(__a, __b, __p) __arm_vorrq_x_u8(__a, __b, __p)
+#define vorrq_x_u16(__a, __b, __p) __arm_vorrq_x_u16(__a, __b, __p)
+#define vorrq_x_u32(__a, __b, __p) __arm_vorrq_x_u32(__a, __b, __p)
+#define vrev16q_x_s8(__a, __p) __arm_vrev16q_x_s8(__a, __p)
+#define vrev16q_x_u8(__a, __p) __arm_vrev16q_x_u8(__a, __p)
+#define vrev32q_x_s8(__a, __p) __arm_vrev32q_x_s8(__a, __p)
+#define vrev32q_x_s16(__a, __p) __arm_vrev32q_x_s16(__a, __p)
+#define vrev32q_x_u8(__a, __p) __arm_vrev32q_x_u8(__a, __p)
+#define vrev32q_x_u16(__a, __p) __arm_vrev32q_x_u16(__a, __p)
+#define vrev64q_x_s8(__a, __p) __arm_vrev64q_x_s8(__a, __p)
+#define vrev64q_x_s16(__a, __p) __arm_vrev64q_x_s16(__a, __p)
+#define vrev64q_x_s32(__a, __p) __arm_vrev64q_x_s32(__a, __p)
+#define vrev64q_x_u8(__a, __p) __arm_vrev64q_x_u8(__a, __p)
+#define vrev64q_x_u16(__a, __p) __arm_vrev64q_x_u16(__a, __p)
+#define vrev64q_x_u32(__a, __p) __arm_vrev64q_x_u32(__a, __p)
+#define vrshlq_x_s8(__a, __b, __p) __arm_vrshlq_x_s8(__a, __b, __p)
+#define vrshlq_x_s16(__a, __b, __p) __arm_vrshlq_x_s16(__a, __b, __p)
+#define vrshlq_x_s32(__a, __b, __p) __arm_vrshlq_x_s32(__a, __b, __p)
+#define vrshlq_x_u8(__a, __b, __p) __arm_vrshlq_x_u8(__a, __b, __p)
+#define vrshlq_x_u16(__a, __b, __p) __arm_vrshlq_x_u16(__a, __b, __p)
+#define vrshlq_x_u32(__a, __b, __p) __arm_vrshlq_x_u32(__a, __b, __p)
+#define vshllbq_x_n_s8(__a, __imm, __p) __arm_vshllbq_x_n_s8(__a, __imm, __p)
+#define vshllbq_x_n_s16(__a, __imm, __p) __arm_vshllbq_x_n_s16(__a, __imm, __p)
+#define vshllbq_x_n_u8(__a, __imm, __p) __arm_vshllbq_x_n_u8(__a, __imm, __p)
+#define vshllbq_x_n_u16(__a, __imm, __p) __arm_vshllbq_x_n_u16(__a, __imm, __p)
+#define vshlltq_x_n_s8(__a, __imm, __p) __arm_vshlltq_x_n_s8(__a, __imm, __p)
+#define vshlltq_x_n_s16(__a, __imm, __p) __arm_vshlltq_x_n_s16(__a, __imm, __p)
+#define vshlltq_x_n_u8(__a, __imm, __p) __arm_vshlltq_x_n_u8(__a, __imm, __p)
+#define vshlltq_x_n_u16(__a, __imm, __p) __arm_vshlltq_x_n_u16(__a, __imm, __p)
+#define vshlq_x_s8(__a, __b, __p) __arm_vshlq_x_s8(__a, __b, __p)
+#define vshlq_x_s16(__a, __b, __p) __arm_vshlq_x_s16(__a, __b, __p)
+#define vshlq_x_s32(__a, __b, __p) __arm_vshlq_x_s32(__a, __b, __p)
+#define vshlq_x_u8(__a, __b, __p) __arm_vshlq_x_u8(__a, __b, __p)
+#define vshlq_x_u16(__a, __b, __p) __arm_vshlq_x_u16(__a, __b, __p)
+#define vshlq_x_u32(__a, __b, __p) __arm_vshlq_x_u32(__a, __b, __p)
+#define vshlq_x_n_s8(__a, __imm, __p) __arm_vshlq_x_n_s8(__a, __imm, __p)
+#define vshlq_x_n_s16(__a, __imm, __p) __arm_vshlq_x_n_s16(__a, __imm, __p)
+#define vshlq_x_n_s32(__a, __imm, __p) __arm_vshlq_x_n_s32(__a, __imm, __p)
+#define vshlq_x_n_u8(__a, __imm, __p) __arm_vshlq_x_n_u8(__a, __imm, __p)
+#define vshlq_x_n_u16(__a, __imm, __p) __arm_vshlq_x_n_u16(__a, __imm, __p)
+#define vshlq_x_n_u32(__a, __imm, __p) __arm_vshlq_x_n_u32(__a, __imm, __p)
+#define vrshrq_x_n_s8(__a, __imm, __p) __arm_vrshrq_x_n_s8(__a, __imm, __p)
+#define vrshrq_x_n_s16(__a, __imm, __p) __arm_vrshrq_x_n_s16(__a, __imm, __p)
+#define vrshrq_x_n_s32(__a, __imm, __p) __arm_vrshrq_x_n_s32(__a, __imm, __p)
+#define vrshrq_x_n_u8(__a, __imm, __p) __arm_vrshrq_x_n_u8(__a, __imm, __p)
+#define vrshrq_x_n_u16(__a, __imm, __p) __arm_vrshrq_x_n_u16(__a, __imm, __p)
+#define vrshrq_x_n_u32(__a, __imm, __p) __arm_vrshrq_x_n_u32(__a, __imm, __p)
+#define vshrq_x_n_s8(__a, __imm, __p) __arm_vshrq_x_n_s8(__a, __imm, __p)
+#define vshrq_x_n_s16(__a, __imm, __p) __arm_vshrq_x_n_s16(__a, __imm, __p)
+#define vshrq_x_n_s32(__a, __imm, __p) __arm_vshrq_x_n_s32(__a, __imm, __p)
+#define vshrq_x_n_u8(__a, __imm, __p) __arm_vshrq_x_n_u8(__a, __imm, __p)
+#define vshrq_x_n_u16(__a, __imm, __p) __arm_vshrq_x_n_u16(__a, __imm, __p)
+#define vshrq_x_n_u32(__a, __imm, __p) __arm_vshrq_x_n_u32(__a, __imm, __p)
+#define vdupq_x_n_f16(__a, __p) __arm_vdupq_x_n_f16(__a, __p)
+#define vdupq_x_n_f32(__a, __p) __arm_vdupq_x_n_f32(__a, __p)
+#define vminnmq_x_f16(__a, __b, __p) __arm_vminnmq_x_f16(__a, __b, __p)
+#define vminnmq_x_f32(__a, __b, __p) __arm_vminnmq_x_f32(__a, __b, __p)
+#define vmaxnmq_x_f16(__a, __b, __p) __arm_vmaxnmq_x_f16(__a, __b, __p)
+#define vmaxnmq_x_f32(__a, __b, __p) __arm_vmaxnmq_x_f32(__a, __b, __p)
+#define vabdq_x_f16(__a, __b, __p) __arm_vabdq_x_f16(__a, __b, __p)
+#define vabdq_x_f32(__a, __b, __p) __arm_vabdq_x_f32(__a, __b, __p)
+#define vabsq_x_f16(__a, __p) __arm_vabsq_x_f16(__a, __p)
+#define vabsq_x_f32(__a, __p) __arm_vabsq_x_f32(__a, __p)
+#define vaddq_x_f16(__a, __b, __p) __arm_vaddq_x_f16(__a, __b, __p)
+#define vaddq_x_f32(__a, __b, __p) __arm_vaddq_x_f32(__a, __b, __p)
+#define vaddq_x_n_f16(__a, __b, __p) __arm_vaddq_x_n_f16(__a, __b, __p)
+#define vaddq_x_n_f32(__a, __b, __p) __arm_vaddq_x_n_f32(__a, __b, __p)
+#define vnegq_x_f16(__a, __p) __arm_vnegq_x_f16(__a, __p)
+#define vnegq_x_f32(__a, __p) __arm_vnegq_x_f32(__a, __p)
+#define vmulq_x_f16(__a, __b, __p) __arm_vmulq_x_f16(__a, __b, __p)
+#define vmulq_x_f32(__a, __b, __p) __arm_vmulq_x_f32(__a, __b, __p)
+#define vmulq_x_n_f16(__a, __b, __p) __arm_vmulq_x_n_f16(__a, __b, __p)
+#define vmulq_x_n_f32(__a, __b, __p) __arm_vmulq_x_n_f32(__a, __b, __p)
+#define vsubq_x_f16(__a, __b, __p) __arm_vsubq_x_f16(__a, __b, __p)
+#define vsubq_x_f32(__a, __b, __p) __arm_vsubq_x_f32(__a, __b, __p)
+#define vsubq_x_n_f16(__a, __b, __p) __arm_vsubq_x_n_f16(__a, __b, __p)
+#define vsubq_x_n_f32(__a, __b, __p) __arm_vsubq_x_n_f32(__a, __b, __p)
+#define vcaddq_rot90_x_f16(__a, __b, __p) __arm_vcaddq_rot90_x_f16(__a, __b, __p)
+#define vcaddq_rot90_x_f32(__a, __b, __p) __arm_vcaddq_rot90_x_f32(__a, __b, __p)
+#define vcaddq_rot270_x_f16(__a, __b, __p) __arm_vcaddq_rot270_x_f16(__a, __b, __p)
+#define vcaddq_rot270_x_f32(__a, __b, __p) __arm_vcaddq_rot270_x_f32(__a, __b, __p)
+#define vcmulq_x_f16(__a, __b, __p) __arm_vcmulq_x_f16(__a, __b, __p)
+#define vcmulq_x_f32(__a, __b, __p) __arm_vcmulq_x_f32(__a, __b, __p)
+#define vcmulq_rot90_x_f16(__a, __b, __p) __arm_vcmulq_rot90_x_f16(__a, __b, __p)
+#define vcmulq_rot90_x_f32(__a, __b, __p) __arm_vcmulq_rot90_x_f32(__a, __b, __p)
+#define vcmulq_rot180_x_f16(__a, __b, __p) __arm_vcmulq_rot180_x_f16(__a, __b, __p)
+#define vcmulq_rot180_x_f32(__a, __b, __p) __arm_vcmulq_rot180_x_f32(__a, __b, __p)
+#define vcmulq_rot270_x_f16(__a, __b, __p) __arm_vcmulq_rot270_x_f16(__a, __b, __p)
+#define vcmulq_rot270_x_f32(__a, __b, __p) __arm_vcmulq_rot270_x_f32(__a, __b, __p)
+#define vcvtaq_x_s16_f16(__a, __p) __arm_vcvtaq_x_s16_f16(__a, __p)
+#define vcvtaq_x_s32_f32(__a, __p) __arm_vcvtaq_x_s32_f32(__a, __p)
+#define vcvtaq_x_u16_f16(__a, __p) __arm_vcvtaq_x_u16_f16(__a, __p)
+#define vcvtaq_x_u32_f32(__a, __p) __arm_vcvtaq_x_u32_f32(__a, __p)
+#define vcvtnq_x_s16_f16(__a, __p) __arm_vcvtnq_x_s16_f16(__a, __p)
+#define vcvtnq_x_s32_f32(__a, __p) __arm_vcvtnq_x_s32_f32(__a, __p)
+#define vcvtnq_x_u16_f16(__a, __p) __arm_vcvtnq_x_u16_f16(__a, __p)
+#define vcvtnq_x_u32_f32(__a, __p) __arm_vcvtnq_x_u32_f32(__a, __p)
+#define vcvtpq_x_s16_f16(__a, __p) __arm_vcvtpq_x_s16_f16(__a, __p)
+#define vcvtpq_x_s32_f32(__a, __p) __arm_vcvtpq_x_s32_f32(__a, __p)
+#define vcvtpq_x_u16_f16(__a, __p) __arm_vcvtpq_x_u16_f16(__a, __p)
+#define vcvtpq_x_u32_f32(__a, __p) __arm_vcvtpq_x_u32_f32(__a, __p)
+#define vcvtmq_x_s16_f16(__a, __p) __arm_vcvtmq_x_s16_f16(__a, __p)
+#define vcvtmq_x_s32_f32(__a, __p) __arm_vcvtmq_x_s32_f32(__a, __p)
+#define vcvtmq_x_u16_f16(__a, __p) __arm_vcvtmq_x_u16_f16(__a, __p)
+#define vcvtmq_x_u32_f32(__a, __p) __arm_vcvtmq_x_u32_f32(__a, __p)
+#define vcvtbq_x_f32_f16(__a, __p) __arm_vcvtbq_x_f32_f16(__a, __p)
+#define vcvttq_x_f32_f16(__a, __p) __arm_vcvttq_x_f32_f16(__a, __p)
+#define vcvtq_x_f16_u16(__a, __p) __arm_vcvtq_x_f16_u16(__a, __p)
+#define vcvtq_x_f16_s16(__a, __p) __arm_vcvtq_x_f16_s16(__a, __p)
+#define vcvtq_x_f32_s32(__a, __p) __arm_vcvtq_x_f32_s32(__a, __p)
+#define vcvtq_x_f32_u32(__a, __p) __arm_vcvtq_x_f32_u32(__a, __p)
+#define vcvtq_x_n_f16_s16(__a, __imm6, __p) __arm_vcvtq_x_n_f16_s16(__a, __imm6, __p)
+#define vcvtq_x_n_f16_u16(__a, __imm6, __p) __arm_vcvtq_x_n_f16_u16(__a, __imm6, __p)
+#define vcvtq_x_n_f32_s32(__a, __imm6, __p) __arm_vcvtq_x_n_f32_s32(__a, __imm6, __p)
+#define vcvtq_x_n_f32_u32(__a, __imm6, __p) __arm_vcvtq_x_n_f32_u32(__a, __imm6, __p)
+#define vcvtq_x_s16_f16(__a, __p) __arm_vcvtq_x_s16_f16(__a, __p)
+#define vcvtq_x_s32_f32(__a, __p) __arm_vcvtq_x_s32_f32(__a, __p)
+#define vcvtq_x_u16_f16(__a, __p) __arm_vcvtq_x_u16_f16(__a, __p)
+#define vcvtq_x_u32_f32(__a, __p) __arm_vcvtq_x_u32_f32(__a, __p)
+#define vcvtq_x_n_s16_f16(__a, __imm6, __p) __arm_vcvtq_x_n_s16_f16(__a, __imm6, __p)
+#define vcvtq_x_n_s32_f32(__a, __imm6, __p) __arm_vcvtq_x_n_s32_f32(__a, __imm6, __p)
+#define vcvtq_x_n_u16_f16(__a, __imm6, __p) __arm_vcvtq_x_n_u16_f16(__a, __imm6, __p)
+#define vcvtq_x_n_u32_f32(__a, __imm6, __p) __arm_vcvtq_x_n_u32_f32(__a, __imm6, __p)
+#define vrndq_x_f16(__a, __p) __arm_vrndq_x_f16(__a, __p)
+#define vrndq_x_f32(__a, __p) __arm_vrndq_x_f32(__a, __p)
+#define vrndnq_x_f16(__a, __p) __arm_vrndnq_x_f16(__a, __p)
+#define vrndnq_x_f32(__a, __p) __arm_vrndnq_x_f32(__a, __p)
+#define vrndmq_x_f16(__a, __p) __arm_vrndmq_x_f16(__a, __p)
+#define vrndmq_x_f32(__a, __p) __arm_vrndmq_x_f32(__a, __p)
+#define vrndpq_x_f16(__a, __p) __arm_vrndpq_x_f16(__a, __p)
+#define vrndpq_x_f32(__a, __p) __arm_vrndpq_x_f32(__a, __p)
+#define vrndaq_x_f16(__a, __p) __arm_vrndaq_x_f16(__a, __p)
+#define vrndaq_x_f32(__a, __p) __arm_vrndaq_x_f32(__a, __p)
+#define vrndxq_x_f16(__a, __p) __arm_vrndxq_x_f16(__a, __p)
+#define vrndxq_x_f32(__a, __p) __arm_vrndxq_x_f32(__a, __p)
+#define vandq_x_f16(__a, __b, __p) __arm_vandq_x_f16(__a, __b, __p)
+#define vandq_x_f32(__a, __b, __p) __arm_vandq_x_f32(__a, __b, __p)
+#define vbicq_x_f16(__a, __b, __p) __arm_vbicq_x_f16(__a, __b, __p)
+#define vbicq_x_f32(__a, __b, __p) __arm_vbicq_x_f32(__a, __b, __p)
+#define vbrsrq_x_n_f16(__a, __b, __p) __arm_vbrsrq_x_n_f16(__a, __b, __p)
+#define vbrsrq_x_n_f32(__a, __b, __p) __arm_vbrsrq_x_n_f32(__a, __b, __p)
+#define veorq_x_f16(__a, __b, __p) __arm_veorq_x_f16(__a, __b, __p)
+#define veorq_x_f32(__a, __b, __p) __arm_veorq_x_f32(__a, __b, __p)
+#define vornq_x_f16(__a, __b, __p) __arm_vornq_x_f16(__a, __b, __p)
+#define vornq_x_f32(__a, __b, __p) __arm_vornq_x_f32(__a, __b, __p)
+#define vorrq_x_f16(__a, __b, __p) __arm_vorrq_x_f16(__a, __b, __p)
+#define vorrq_x_f32(__a, __b, __p) __arm_vorrq_x_f32(__a, __b, __p)
+#define vrev32q_x_f16(__a, __p) __arm_vrev32q_x_f16(__a, __p)
+#define vrev64q_x_f16(__a, __p) __arm_vrev64q_x_f16(__a, __p)
+#define vrev64q_x_f32(__a, __p) __arm_vrev64q_x_f32(__a, __p)
#endif
__extension__ extern __inline void
@@ -13552,2676 +13928,5344 @@ __arm_vstrwq_scatter_base_wb_u32 (uint32x4_t * __addr, const int __offset, uint3
__builtin_mve_vstrwq_scatter_base_wb_add_uv4si (*__addr, __offset, *__addr);
}
-#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vddupq_x_n_u8 (uint32_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vddupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p);
+}
-__extension__ extern __inline void
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value)
+__arm_vddupq_x_n_u16 (uint32_t __a, const int __imm, mve_pred16_t __p)
{
- union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__i = __value;
- __builtin_mve_vst4qv8hf (__addr, __rv.__o);
+ return __builtin_mve_vddupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value)
+__arm_vddupq_x_n_u32 (uint32_t __a, const int __imm, mve_pred16_t __p)
{
- union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv;
- __rv.__i = __value;
- __builtin_mve_vst4qv4sf (__addr, __rv.__o);
+ return __builtin_mve_vddupq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndxq_f16 (float16x8_t __a)
+__arm_vddupq_x_wb_u8 (uint32_t *__a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndxq_fv8hf (__a);
+ uint8x16_t __arg1 = vuninitializedq_u8 ();
+ uint8x16_t __res = __builtin_mve_vddupq_m_n_uv16qi (__arg1, * __a, __imm, __p);
+ *__a -= __imm * 16u;
+ return __res;
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndxq_f32 (float32x4_t __a)
+__arm_vddupq_x_wb_u16 (uint32_t *__a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndxq_fv4sf (__a);
+ uint16x8_t __arg1 = vuninitializedq_u16 ();
+ uint16x8_t __res = __builtin_mve_vddupq_m_n_uv8hi (__arg1, *__a, __imm, __p);
+ *__a -= __imm * 8u;
+ return __res;
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndq_f16 (float16x8_t __a)
+__arm_vddupq_x_wb_u32 (uint32_t *__a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndq_fv8hf (__a);
+ uint32x4_t __arg1 = vuninitializedq_u32 ();
+ uint32x4_t __res = __builtin_mve_vddupq_m_n_uv4si (__arg1, *__a, __imm, __p);
+ *__a -= __imm * 4u;
+ return __res;
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndq_f32 (float32x4_t __a)
+__arm_vdwdupq_x_n_u8 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndq_fv4sf (__a);
+ return __builtin_mve_vdwdupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndpq_f16 (float16x8_t __a)
+__arm_vdwdupq_x_n_u16 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndpq_fv8hf (__a);
+ return __builtin_mve_vdwdupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __imm, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndpq_f32 (float32x4_t __a)
+__arm_vdwdupq_x_n_u32 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndpq_fv4sf (__a);
+ return __builtin_mve_vdwdupq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndnq_f16 (float16x8_t __a)
+__arm_vdwdupq_x_wb_u8 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndnq_fv8hf (__a);
+ uint8x16_t __arg1 = vuninitializedq_u8 ();
+ uint8x16_t __res = __builtin_mve_vdwdupq_m_n_uv16qi (__arg1, *__a, __b, __imm, __p);
+ *__a = __builtin_mve_vdwdupq_m_wb_uv16qi (__arg1, *__a, __b, __imm, __p);
+ return __res;
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndnq_f32 (float32x4_t __a)
+__arm_vdwdupq_x_wb_u16 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndnq_fv4sf (__a);
+ uint16x8_t __arg1 = vuninitializedq_u16 ();
+ uint16x8_t __res = __builtin_mve_vdwdupq_m_n_uv8hi (__arg1, *__a, __b, __imm, __p);
+ *__a = __builtin_mve_vdwdupq_m_wb_uv8hi (__arg1, *__a, __b, __imm, __p);
+ return __res;
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndmq_f16 (float16x8_t __a)
+__arm_vdwdupq_x_wb_u32 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndmq_fv8hf (__a);
+ uint32x4_t __arg1 = vuninitializedq_u32 ();
+ uint32x4_t __res = __builtin_mve_vdwdupq_m_n_uv4si (__arg1, *__a, __b, __imm, __p);
+ *__a = __builtin_mve_vdwdupq_m_wb_uv4si (__arg1, *__a, __b, __imm, __p);
+ return __res;
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndmq_f32 (float32x4_t __a)
+__arm_vidupq_x_n_u8 (uint32_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndmq_fv4sf (__a);
+ return __builtin_mve_vidupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndaq_f16 (float16x8_t __a)
+__arm_vidupq_x_n_u16 (uint32_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndaq_fv8hf (__a);
+ return __builtin_mve_vidupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndaq_f32 (float32x4_t __a)
+__arm_vidupq_x_n_u32 (uint32_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrndaq_fv4sf (__a);
+ return __builtin_mve_vidupq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrev64q_f16 (float16x8_t __a)
+__arm_vidupq_x_wb_u8 (uint32_t *__a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrev64q_fv8hf (__a);
+ uint8x16_t __arg1 = vuninitializedq_u8 ();
+ uint8x16_t __res = __builtin_mve_vidupq_m_n_uv16qi (__arg1, *__a, __imm, __p);
+ *__a += __imm * 16u;
+ return __res;
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrev64q_f32 (float32x4_t __a)
+__arm_vidupq_x_wb_u16 (uint32_t *__a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrev64q_fv4sf (__a);
+ uint16x8_t __arg1 = vuninitializedq_u16 ();
+ uint16x8_t __res = __builtin_mve_vidupq_m_n_uv8hi (__arg1, *__a, __imm, __p);
+ *__a += __imm * 8u;
+ return __res;
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vnegq_f16 (float16x8_t __a)
+__arm_vidupq_x_wb_u32 (uint32_t *__a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vnegq_fv8hf (__a);
+ uint32x4_t __arg1 = vuninitializedq_u32 ();
+ uint32x4_t __res = __builtin_mve_vidupq_m_n_uv4si (__arg1, *__a, __imm, __p);
+ *__a += __imm * 4u;
+ return __res;
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vnegq_f32 (float32x4_t __a)
+__arm_viwdupq_x_n_u8 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vnegq_fv4sf (__a);
+ return __builtin_mve_viwdupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vdupq_n_f16 (float16_t __a)
+__arm_viwdupq_x_n_u16 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vdupq_n_fv8hf (__a);
+ return __builtin_mve_viwdupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __imm, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vdupq_n_f32 (float32_t __a)
+__arm_viwdupq_x_n_u32 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vdupq_n_fv4sf (__a);
+ return __builtin_mve_viwdupq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vabsq_f16 (float16x8_t __a)
+__arm_viwdupq_x_wb_u8 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vabsq_fv8hf (__a);
+ uint8x16_t __arg1 = vuninitializedq_u8 ();
+ uint8x16_t __res = __builtin_mve_viwdupq_m_n_uv16qi (__arg1, *__a, __b, __imm, __p);
+ *__a = __builtin_mve_viwdupq_m_wb_uv16qi (__arg1, *__a, __b, __imm, __p);
+ return __res;
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vabsq_f32 (float32x4_t __a)
+__arm_viwdupq_x_wb_u16 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vabsq_fv4sf (__a);
+ uint16x8_t __arg1 = vuninitializedq_u16 ();
+ uint16x8_t __res = __builtin_mve_viwdupq_m_n_uv8hi (__arg1, *__a, __b, __imm, __p);
+ *__a = __builtin_mve_viwdupq_m_wb_uv8hi (__arg1, *__a, __b, __imm, __p);
+ return __res;
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrev32q_f16 (float16x8_t __a)
+__arm_viwdupq_x_wb_u32 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vrev32q_fv8hf (__a);
+ uint32x4_t __arg1 = vuninitializedq_u32 ();
+ uint32x4_t __res = __builtin_mve_viwdupq_m_n_uv4si (__arg1, *__a, __b, __imm, __p);
+ *__a = __builtin_mve_viwdupq_m_wb_uv4si (__arg1, *__a, __b, __imm, __p);
+ return __res;
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvttq_f32_f16 (float16x8_t __a)
+__arm_vdupq_x_n_s8 (int8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvttq_f32_f16v4sf (__a);
+ return __builtin_mve_vdupq_m_n_sv16qi (vuninitializedq_s8 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtbq_f32_f16 (float16x8_t __a)
+__arm_vdupq_x_n_s16 (int16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtbq_f32_f16v4sf (__a);
+ return __builtin_mve_vdupq_m_n_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_f16_s16 (int16x8_t __a)
+__arm_vdupq_x_n_s32 (int32_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_to_f_sv8hf (__a);
+ return __builtin_mve_vdupq_m_n_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_f32_s32 (int32x4_t __a)
+__arm_vdupq_x_n_u8 (uint8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_to_f_sv4sf (__a);
+ return __builtin_mve_vdupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_f16_u16 (uint16x8_t __a)
+__arm_vdupq_x_n_u16 (uint16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_to_f_uv8hf (__a);
+ return __builtin_mve_vdupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_f32_u32 (uint32x4_t __a)
+__arm_vdupq_x_n_u32 (uint32_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_to_f_uv4sf (__a);
+ return __builtin_mve_vdupq_m_n_uv4si (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_s16_f16 (float16x8_t __a)
+__arm_vminq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_from_f_sv8hi (__a);
+ return __builtin_mve_vminq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_s32_f32 (float32x4_t __a)
+__arm_vminq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_from_f_sv4si (__a);
+ return __builtin_mve_vminq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_u16_f16 (float16x8_t __a)
+__arm_vminq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_from_f_uv8hi (__a);
+ return __builtin_mve_vminq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_u32_f32 (float32x4_t __a)
+__arm_vminq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_from_f_uv4si (__a);
+ return __builtin_mve_vminq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtpq_u16_f16 (float16x8_t __a)
+__arm_vminq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtpq_uv8hi (__a);
+ return __builtin_mve_vminq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtpq_u32_f32 (float32x4_t __a)
+__arm_vminq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtpq_uv4si (__a);
+ return __builtin_mve_vminq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtnq_u16_f16 (float16x8_t __a)
+__arm_vmaxq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtnq_uv8hi (__a);
+ return __builtin_mve_vmaxq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtmq_u16_f16 (float16x8_t __a)
+__arm_vmaxq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtmq_uv8hi (__a);
+ return __builtin_mve_vmaxq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtmq_u32_f32 (float32x4_t __a)
+__arm_vmaxq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtmq_uv4si (__a);
+ return __builtin_mve_vmaxq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtaq_u16_f16 (float16x8_t __a)
+__arm_vmaxq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtaq_uv8hi (__a);
+ return __builtin_mve_vmaxq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtaq_u32_f32 (float32x4_t __a)
+__arm_vmaxq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtaq_uv4si (__a);
+ return __builtin_mve_vmaxq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vabdq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtaq_s16_f16 (float16x8_t __a)
+__arm_vabdq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtaq_sv8hi (__a);
+ return __builtin_mve_vabdq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtaq_s32_f32 (float32x4_t __a)
+__arm_vabdq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtaq_sv4si (__a);
+ return __builtin_mve_vabdq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtnq_s16_f16 (float16x8_t __a)
+__arm_vabdq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtnq_sv8hi (__a);
+ return __builtin_mve_vabdq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtnq_s32_f32 (float32x4_t __a)
+__arm_vabdq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtnq_sv4si (__a);
+ return __builtin_mve_vabdq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtpq_s16_f16 (float16x8_t __a)
+__arm_vabdq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtpq_sv8hi (__a);
+ return __builtin_mve_vabdq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtpq_s32_f32 (float32x4_t __a)
+__arm_vabsq_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtpq_sv4si (__a);
+ return __builtin_mve_vabsq_m_sv16qi (vuninitializedq_s8 (), __a, __p);
}
__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtmq_s16_f16 (float16x8_t __a)
+__arm_vabsq_x_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtmq_sv8hi (__a);
+ return __builtin_mve_vabsq_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtmq_s32_f32 (float32x4_t __a)
+__arm_vabsq_x_s32 (int32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtmq_sv4si (__a);
+ return __builtin_mve_vabsq_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vsubq_n_f16 (float16x8_t __a, float16_t __b)
+__arm_vaddq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vsubq_n_fv8hf (__a, __b);
+ return __builtin_mve_vaddq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vsubq_n_f32 (float32x4_t __a, float32_t __b)
+__arm_vaddq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vsubq_n_fv4sf (__a, __b);
+ return __builtin_mve_vaddq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vbrsrq_n_f16 (float16x8_t __a, int32_t __b)
+__arm_vaddq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vbrsrq_n_fv8hf (__a, __b);
+ return __builtin_mve_vaddq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vbrsrq_n_f32 (float32x4_t __a, int32_t __b)
+__arm_vaddq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vbrsrq_n_fv4sf (__a, __b);
+ return __builtin_mve_vaddq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_n_f16_s16 (int16x8_t __a, const int __imm6)
+__arm_vaddq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_n_to_f_sv8hf (__a, __imm6);
+ return __builtin_mve_vaddq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_n_f32_s32 (int32x4_t __a, const int __imm6)
+__arm_vaddq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_n_to_f_sv4sf (__a, __imm6);
+ return __builtin_mve_vaddq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_n_f16_u16 (uint16x8_t __a, const int __imm6)
+__arm_vaddq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_n_to_f_uv8hf (__a, __imm6);
+ return __builtin_mve_vaddq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_n_f32_u32 (uint32x4_t __a, const int __imm6)
+__arm_vaddq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_n_to_f_uv4sf (__a, __imm6);
+ return __builtin_mve_vaddq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcreateq_f16 (uint64_t __a, uint64_t __b)
+__arm_vaddq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcreateq_fv8hf (__a, __b);
+ return __builtin_mve_vaddq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcreateq_f32 (uint64_t __a, uint64_t __b)
+__arm_vaddq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcreateq_fv4sf (__a, __b);
+ return __builtin_mve_vaddq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6)
+__arm_vaddq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6);
+ return __builtin_mve_vaddq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6)
+__arm_vaddq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6);
+ return __builtin_mve_vaddq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6)
+__arm_vclsq_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6);
+ return __builtin_mve_vclsq_m_sv16qi (vuninitializedq_s8 (), __a, __p);
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6)
+__arm_vclsq_x_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6);
+ return __builtin_mve_vclsq_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpneq_n_f16 (float16x8_t __a, float16_t __b)
+__arm_vclsq_x_s32 (int32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpneq_n_fv8hf (__a, __b);
+ return __builtin_mve_vclsq_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpneq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vclzq_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpneq_fv8hf (__a, __b);
+ return __builtin_mve_vclzq_m_sv16qi (vuninitializedq_s8 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpltq_n_f16 (float16x8_t __a, float16_t __b)
+__arm_vclzq_x_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpltq_n_fv8hf (__a, __b);
+ return __builtin_mve_vclzq_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpltq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vclzq_x_s32 (int32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpltq_fv8hf (__a, __b);
+ return __builtin_mve_vclzq_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpleq_n_f16 (float16x8_t __a, float16_t __b)
+__arm_vclzq_x_u8 (uint8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpleq_n_fv8hf (__a, __b);
+ return __builtin_mve_vclzq_m_uv16qi (vuninitializedq_u8 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpleq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vclzq_x_u16 (uint16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpleq_fv8hf (__a, __b);
+ return __builtin_mve_vclzq_m_uv8hi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgtq_n_f16 (float16x8_t __a, float16_t __b)
+__arm_vclzq_x_u32 (uint32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgtq_n_fv8hf (__a, __b);
+ return __builtin_mve_vclzq_m_uv4si (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgtq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vnegq_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgtq_fv8hf (__a, __b);
+ return __builtin_mve_vnegq_m_sv16qi (vuninitializedq_s8 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgeq_n_f16 (float16x8_t __a, float16_t __b)
+__arm_vnegq_x_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgeq_n_fv8hf (__a, __b);
+ return __builtin_mve_vnegq_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgeq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vnegq_x_s32 (int32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgeq_fv8hf (__a, __b);
+ return __builtin_mve_vnegq_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpeqq_n_f16 (float16x8_t __a, float16_t __b)
+__arm_vmulhq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpeqq_n_fv8hf (__a, __b);
+ return __builtin_mve_vmulhq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpeqq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulhq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpeqq_fv8hf (__a, __b);
+ return __builtin_mve_vmulhq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vsubq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulhq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vsubq_fv8hf (__a, __b);
+ return __builtin_mve_vmulhq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vorrq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulhq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vorrq_fv8hf (__a, __b);
+ return __builtin_mve_vmulhq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vornq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulhq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vornq_fv8hf (__a, __b);
+ return __builtin_mve_vmulhq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmulq_n_f16 (float16x8_t __a, float16_t __b)
+__arm_vmulhq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmulq_n_fv8hf (__a, __b);
+ return __builtin_mve_vmulhq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmulq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmullbq_poly_x_p8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmulq_fv8hf (__a, __b);
+ return __builtin_mve_vmullbq_poly_m_pv16qi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_f16 (float16_t __a, float16x8_t __b)
+__arm_vmullbq_poly_x_p16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmvq_fv8hf (__a, __b);
+ return __builtin_mve_vmullbq_poly_m_pv8hi (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmullbq_int_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmq_fv8hf (__a, __b);
+ return __builtin_mve_vmullbq_int_m_sv16qi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_f16 (float16_t __a, float16x8_t __b)
+__arm_vmullbq_int_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmavq_fv8hf (__a, __b);
+ return __builtin_mve_vmullbq_int_m_sv8hi (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int64x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmullbq_int_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmaq_fv8hf (__a, __b);
+ return __builtin_mve_vmullbq_int_m_sv4si (vuninitializedq_s64 (), __a, __b, __p);
}
-__extension__ extern __inline float16_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_f16 (float16_t __a, float16x8_t __b)
+__arm_vmullbq_int_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmvq_fv8hf (__a, __b);
+ return __builtin_mve_vmullbq_int_m_uv16qi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmullbq_int_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmq_fv8hf (__a, __b);
+ return __builtin_mve_vmullbq_int_m_uv8hi (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16_t
+__extension__ extern __inline uint64x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_f16 (float16_t __a, float16x8_t __b)
+__arm_vmullbq_int_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmavq_fv8hf (__a, __b);
+ return __builtin_mve_vmullbq_int_m_uv4si (vuninitializedq_u64 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulltq_poly_x_p8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmaq_fv8hf (__a, __b);
+ return __builtin_mve_vmulltq_poly_m_pv16qi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_veorq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulltq_poly_x_p16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_veorq_fv8hf (__a, __b);
+ return __builtin_mve_vmulltq_poly_m_pv8hi (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot90_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulltq_int_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmulq_rot90_fv8hf (__a, __b);
+ return __builtin_mve_vmulltq_int_m_sv16qi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot270_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulltq_int_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmulq_rot270_fv8hf (__a, __b);
+ return __builtin_mve_vmulltq_int_m_sv8hi (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int64x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot180_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulltq_int_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmulq_rot180_fv8hf (__a, __b);
+ return __builtin_mve_vmulltq_int_m_sv4si (vuninitializedq_s64 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulltq_int_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmulq_fv8hf (__a, __b);
+ return __builtin_mve_vmulltq_int_m_uv16qi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulltq_int_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcaddq_rot90_fv8hf (__a, __b);
+ return __builtin_mve_vmulltq_int_m_uv8hi (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint64x2_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulltq_int_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcaddq_rot270_fv8hf (__a, __b);
+ return __builtin_mve_vmulltq_int_m_uv4si (vuninitializedq_u64 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vbicq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vbicq_fv8hf (__a, __b);
+ return __builtin_mve_vmulq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vandq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vandq_fv8hf (__a, __b);
+ return __builtin_mve_vmulq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_n_f16 (float16x8_t __a, float16_t __b)
+__arm_vmulq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vaddq_n_fv8hf (__a, __b);
+ return __builtin_mve_vmulq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vabdq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vmulq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vabdq_fv8hf (__a, __b);
+ return __builtin_mve_vmulq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpneq_n_f32 (float32x4_t __a, float32_t __b)
+__arm_vmulq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpneq_n_fv4sf (__a, __b);
+ return __builtin_mve_vmulq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpneq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vmulq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpneq_fv4sf (__a, __b);
+ return __builtin_mve_vmulq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpltq_n_f32 (float32x4_t __a, float32_t __b)
+__arm_vmulq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpltq_n_fv4sf (__a, __b);
+ return __builtin_mve_vmulq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpltq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vmulq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpltq_fv4sf (__a, __b);
+ return __builtin_mve_vmulq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpleq_n_f32 (float32x4_t __a, float32_t __b)
+__arm_vmulq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpleq_n_fv4sf (__a, __b);
+ return __builtin_mve_vmulq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpleq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vmulq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpleq_fv4sf (__a, __b);
+ return __builtin_mve_vmulq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgtq_n_f32 (float32x4_t __a, float32_t __b)
+__arm_vmulq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgtq_n_fv4sf (__a, __b);
+ return __builtin_mve_vmulq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgtq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vmulq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgtq_fv4sf (__a, __b);
+ return __builtin_mve_vmulq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgeq_n_f32 (float32x4_t __a, float32_t __b)
+__arm_vsubq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgeq_n_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgeq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vsubq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgeq_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpeqq_n_f32 (float32x4_t __a, float32_t __b)
+__arm_vsubq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpeqq_n_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpeqq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vsubq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpeqq_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vsubq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vsubq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vsubq_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vorrq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vsubq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vorrq_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vornq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vsubq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vornq_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmulq_n_f32 (float32x4_t __a, float32_t __b)
+__arm_vsubq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmulq_n_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmulq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vsubq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmulq_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float32_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_f32 (float32_t __a, float32x4_t __b)
+__arm_vsubq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmvq_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vsubq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmq_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float32_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_f32 (float32_t __a, float32x4_t __b)
+__arm_vsubq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmavq_fv4sf (__a, __b);
+ return __builtin_mve_vsubq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot90_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmaq_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot90_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float32_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_f32 (float32_t __a, float32x4_t __b)
+__arm_vcaddq_rot90_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmvq_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot90_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot90_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmq_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot90_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float32_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_f32 (float32_t __a, float32x4_t __b)
+__arm_vcaddq_rot90_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmavq_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot90_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot90_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmaq_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot90_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_veorq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot90_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_veorq_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot90_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot90_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot270_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmulq_rot90_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot270_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot270_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot270_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmulq_rot270_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot270_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot180_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot270_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmulq_rot180_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot270_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot270_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmulq_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot270_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot270_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcaddq_rot90_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot270_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcaddq_rot270_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcaddq_rot270_fv4sf (__a, __b);
+ return __builtin_mve_vcaddq_rot270_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vbicq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vhaddq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vbicq_fv4sf (__a, __b);
+ return __builtin_mve_vhaddq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vandq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vhaddq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vandq_fv4sf (__a, __b);
+ return __builtin_mve_vhaddq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_n_f32 (float32x4_t __a, float32_t __b)
+__arm_vhaddq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vaddq_n_fv4sf (__a, __b);
+ return __builtin_mve_vhaddq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vabdq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vhaddq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vabdq_fv4sf (__a, __b);
+ return __builtin_mve_vhaddq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvttq_f16_f32 (float16x8_t __a, float32x4_t __b)
+__arm_vhaddq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvttq_f16_f32v8hf (__a, __b);
+ return __builtin_mve_vhaddq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtbq_f16_f32 (float16x8_t __a, float32x4_t __b)
+__arm_vhaddq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtbq_f16_f32v8hf (__a, __b);
+ return __builtin_mve_vhaddq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpeqq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vhaddq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpeqq_m_fv8hf (__a, __b, __p);
+ return __builtin_mve_vhaddq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpeqq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vhaddq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpeqq_m_fv4sf (__a, __b, __p);
+ return __builtin_mve_vhaddq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtaq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vhaddq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtaq_m_sv8hi (__inactive, __a, __p);
+ return __builtin_mve_vhaddq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtaq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vhaddq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtaq_m_uv8hi (__inactive, __a, __p);
+ return __builtin_mve_vhaddq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtaq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vhaddq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtaq_m_sv4si (__inactive, __a, __p);
+ return __builtin_mve_vhaddq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtaq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vhaddq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtaq_m_uv4si (__inactive, __a, __p);
+ return __builtin_mve_vhaddq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_f16_s16 (float16x8_t __inactive, int16x8_t __a, mve_pred16_t __p)
+__arm_vhcaddq_rot90_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_to_f_sv8hf (__inactive, __a, __p);
+ return __builtin_mve_vhcaddq_rot90_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_f16_u16 (float16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p)
+__arm_vhcaddq_rot90_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_to_f_uv8hf (__inactive, __a, __p);
+ return __builtin_mve_vhcaddq_rot90_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_f32_s32 (float32x4_t __inactive, int32x4_t __a, mve_pred16_t __p)
+__arm_vhcaddq_rot90_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_to_f_sv4sf (__inactive, __a, __p);
+ return __builtin_mve_vhcaddq_rot90_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_f32_u32 (float32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p)
+__arm_vhcaddq_rot270_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_to_f_uv4sf (__inactive, __a, __p);
+ return __builtin_mve_vhcaddq_rot270_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtbq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vhcaddq_rot270_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtbq_m_f16_f32v8hf (__a, __b, __p);
+ return __builtin_mve_vhcaddq_rot270_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtbq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vhcaddq_rot270_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtbq_m_f32_f16v4sf (__inactive, __a, __p);
+ return __builtin_mve_vhcaddq_rot270_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvttq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vhsubq_x_n_s8 (int8x16_t __a, int8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvttq_m_f16_f32v8hf (__a, __b, __p);
+ return __builtin_mve_vhsubq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvttq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vhsubq_x_n_s16 (int16x8_t __a, int16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvttq_m_f32_f16v4sf (__inactive, __a, __p);
+ return __builtin_mve_vhsubq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrev32q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vhsubq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrev32q_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vhsubq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+__arm_vhsubq_x_n_u8 (uint8x16_t __a, uint8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmlaq_fv8hf (__a, __b, __c);
+ return __builtin_mve_vhsubq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot180_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+__arm_vhsubq_x_n_u16 (uint16x8_t __a, uint16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmlaq_rot180_fv8hf (__a, __b, __c);
+ return __builtin_mve_vhsubq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot270_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+__arm_vhsubq_x_n_u32 (uint32x4_t __a, uint32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmlaq_rot270_fv8hf (__a, __b, __c);
+ return __builtin_mve_vhsubq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot90_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+__arm_vhsubq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmlaq_rot90_fv8hf (__a, __b, __c);
+ return __builtin_mve_vhsubq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+__arm_vhsubq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vfmaq_fv8hf (__a, __b, __c);
+ return __builtin_mve_vhsubq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmaq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
+__arm_vhsubq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vfmaq_n_fv8hf (__a, __b, __c);
+ return __builtin_mve_vhsubq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmasq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
+__arm_vhsubq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vfmasq_n_fv8hf (__a, __b, __c);
+ return __builtin_mve_vhsubq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+__arm_vhsubq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vfmsq_fv8hf (__a, __b, __c);
+ return __builtin_mve_vhsubq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vabsq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vhsubq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vabsq_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vhsubq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtmq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vrhaddq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtmq_m_sv8hi (__inactive, __a, __p);
+ return __builtin_mve_vrhaddq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtnq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vrhaddq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtnq_m_sv8hi (__inactive, __a, __p);
+ return __builtin_mve_vrhaddq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtpq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vrhaddq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtpq_m_sv8hi (__inactive, __a, __p);
+ return __builtin_mve_vrhaddq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vrhaddq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_from_f_sv8hi (__inactive, __a, __p);
+ return __builtin_mve_vrhaddq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vdupq_m_n_f16 (float16x8_t __inactive, float16_t __a, mve_pred16_t __p)
+__arm_vrhaddq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vdupq_m_n_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vrhaddq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vrhaddq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmaq_m_fv8hf (__a, __b, __p);
+ return __builtin_mve_vrhaddq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vrmulhq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmavq_p_fv8hf (__a, __b, __p);
+ return __builtin_mve_vrmulhq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vrmulhq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmvq_p_fv8hf (__a, __b, __p);
+ return __builtin_mve_vrmulhq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vrmulhq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmaq_m_fv8hf (__a, __b, __p);
+ return __builtin_mve_vrmulhq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vrmulhq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmavq_p_fv8hf (__a, __b, __p);
+ return __builtin_mve_vrmulhq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float16_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vrmulhq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmvq_p_fv8hf (__a, __b, __p);
+ return __builtin_mve_vrmulhq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vnegq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vrmulhq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vnegq_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vrmulhq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vpselq_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vandq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vpselq_fv8hf (__a, __b, __p);
+ return __builtin_mve_vandq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrev64q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vandq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrev64q_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vandq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndaq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vandq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndaq_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vandq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndmq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vandq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndmq_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vandq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndnq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vandq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndnq_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vandq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndpq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vandq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndpq_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vandq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vbicq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndq_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vbicq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndxq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_vbicq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndxq_m_fv8hf (__inactive, __a, __p);
+ return __builtin_mve_vbicq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpeqq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+__arm_vbicq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpeqq_m_n_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbicq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgeq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vbicq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgeq_m_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbicq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgeq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+__arm_vbicq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgeq_m_n_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbicq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgtq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vbicq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgtq_m_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbicq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgtq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+__arm_vbrsrq_x_n_s8 (int8x16_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgtq_m_n_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbrsrq_m_n_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpleq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vbrsrq_x_n_s16 (int16x8_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpleq_m_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbrsrq_m_n_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpleq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+__arm_vbrsrq_x_n_s32 (int32x4_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpleq_m_n_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbrsrq_m_n_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpltq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vbrsrq_x_n_u8 (uint8x16_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpltq_m_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbrsrq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpltq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+__arm_vbrsrq_x_n_u16 (uint16x8_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpltq_m_n_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbrsrq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpneq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vbrsrq_x_n_u32 (uint32x4_t __a, int32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpneq_m_fv8hf (__a, __b, __p);
+ return __builtin_mve_vbrsrq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpneq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+__arm_veorq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpneq_m_n_fv8hf (__a, __b, __p);
+ return __builtin_mve_veorq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtmq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_veorq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtmq_m_uv8hi (__inactive, __a, __p);
+ return __builtin_mve_veorq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtnq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_veorq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtnq_m_uv8hi (__inactive, __a, __p);
+ return __builtin_mve_veorq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtpq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_veorq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtpq_m_uv8hi (__inactive, __a, __p);
+ return __builtin_mve_veorq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+__arm_veorq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_from_f_uv8hi (__inactive, __a, __p);
+ return __builtin_mve_veorq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+__arm_veorq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmlaq_fv4sf (__a, __b, __c);
+ return __builtin_mve_veorq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot180_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+__arm_vmovlbq_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmlaq_rot180_fv4sf (__a, __b, __c);
+ return __builtin_mve_vmovlbq_m_sv16qi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot270_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+__arm_vmovlbq_x_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmlaq_rot270_fv4sf (__a, __b, __c);
+ return __builtin_mve_vmovlbq_m_sv8hi (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot90_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+__arm_vmovlbq_x_u8 (uint8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmlaq_rot90_fv4sf (__a, __b, __c);
+ return __builtin_mve_vmovlbq_m_uv16qi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+__arm_vmovlbq_x_u16 (uint16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vfmaq_fv4sf (__a, __b, __c);
+ return __builtin_mve_vmovlbq_m_uv8hi (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+__arm_vmovltq_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vfmaq_n_fv4sf (__a, __b, __c);
+ return __builtin_mve_vmovltq_m_sv16qi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmasq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+__arm_vmovltq_x_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vfmasq_n_fv4sf (__a, __b, __c);
+ return __builtin_mve_vmovltq_m_sv8hi (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+__arm_vmovltq_x_u8 (uint8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vfmsq_fv4sf (__a, __b, __c);
+ return __builtin_mve_vmovltq_m_uv16qi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vabsq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vmovltq_x_u16 (uint16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vabsq_m_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vmovltq_m_uv8hi (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtmq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vmvnq_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtmq_m_sv4si (__inactive, __a, __p);
+ return __builtin_mve_vmvnq_m_sv16qi (vuninitializedq_s8 (), __a, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtnq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vmvnq_x_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtnq_m_sv4si (__inactive, __a, __p);
+ return __builtin_mve_vmvnq_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtpq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vmvnq_x_s32 (int32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtpq_m_sv4si (__inactive, __a, __p);
+ return __builtin_mve_vmvnq_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vmvnq_x_u8 (uint8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_from_f_sv4si (__inactive, __a, __p);
+ return __builtin_mve_vmvnq_m_uv16qi (vuninitializedq_u8 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vdupq_m_n_f32 (float32x4_t __inactive, float32_t __a, mve_pred16_t __p)
+__arm_vmvnq_x_u16 (uint16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vdupq_m_n_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vmvnq_m_uv8hi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vmvnq_x_u32 (uint32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmaq_m_fv4sf (__a, __b, __p);
+ return __builtin_mve_vmvnq_m_uv4si (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline float32_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vmvnq_x_n_s16 (const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmavq_p_fv4sf (__a, __b, __p);
+ return __builtin_mve_vmvnq_m_n_sv8hi (vuninitializedq_s16 (), __imm, __p);
}
-__extension__ extern __inline float32_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vmvnq_x_n_s32 (const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmvq_p_fv4sf (__a, __b, __p);
+ return __builtin_mve_vmvnq_m_n_sv4si (vuninitializedq_s32 (), __imm, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vmvnq_x_n_u16 (const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vminnmaq_m_fv4sf (__a, __b, __p);
+ return __builtin_mve_vmvnq_m_n_uv8hi (vuninitializedq_u16 (), __imm, __p);
}
-__extension__ extern __inline float32_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vmvnq_x_n_u32 (const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vminnmavq_p_fv4sf (__a, __b, __p);
+ return __builtin_mve_vmvnq_m_n_uv4si (vuninitializedq_u32 (), __imm, __p);
}
-__extension__ extern __inline float32_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vornq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmvq_p_fv4sf (__a, __b, __p);
+ return __builtin_mve_vornq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vnegq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vornq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vnegq_m_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vornq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vpselq_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vornq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vpselq_fv4sf (__a, __b, __p);
+ return __builtin_mve_vornq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrev64q_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vornq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrev64q_m_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vornq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndaq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vornq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndaq_m_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vornq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndmq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vornq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndmq_m_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vornq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndnq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vorrq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndnq_m_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vorrq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndpq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vorrq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndpq_m_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vorrq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vorrq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndq_m_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vorrq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vrndxq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vorrq_x_u8 (uint8x16_t __a, uint8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vrndxq_m_fv4sf (__inactive, __a, __p);
+ return __builtin_mve_vorrq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpeqq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+__arm_vorrq_x_u16 (uint16x8_t __a, uint16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpeqq_m_n_fv4sf (__a, __b, __p);
+ return __builtin_mve_vorrq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgeq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vorrq_x_u32 (uint32x4_t __a, uint32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgeq_m_fv4sf (__a, __b, __p);
+ return __builtin_mve_vorrq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgeq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+__arm_vrev16q_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgeq_m_n_fv4sf (__a, __b, __p);
+ return __builtin_mve_vrev16q_m_sv16qi (vuninitializedq_s8 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgtq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vrev16q_x_u8 (uint8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgtq_m_fv4sf (__a, __b, __p);
+ return __builtin_mve_vrev16q_m_uv16qi (vuninitializedq_u8 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpgtq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+__arm_vrev32q_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpgtq_m_n_fv4sf (__a, __b, __p);
+ return __builtin_mve_vrev32q_m_sv16qi (vuninitializedq_s8 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpleq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vrev32q_x_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpleq_m_fv4sf (__a, __b, __p);
+ return __builtin_mve_vrev32q_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpleq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+__arm_vrev32q_x_u8 (uint8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpleq_m_n_fv4sf (__a, __b, __p);
+ return __builtin_mve_vrev32q_m_uv16qi (vuninitializedq_u8 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpltq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vrev32q_x_u16 (uint16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpltq_m_fv4sf (__a, __b, __p);
+ return __builtin_mve_vrev32q_m_uv8hi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpltq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+__arm_vrev64q_x_s8 (int8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpltq_m_n_fv4sf (__a, __b, __p);
+ return __builtin_mve_vrev64q_m_sv16qi (vuninitializedq_s8 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpneq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vrev64q_x_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpneq_m_fv4sf (__a, __b, __p);
+ return __builtin_mve_vrev64q_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline mve_pred16_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmpneq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+__arm_vrev64q_x_s32 (int32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcmpneq_m_n_fv4sf (__a, __b, __p);
+ return __builtin_mve_vrev64q_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtmq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vrev64q_x_u8 (uint8x16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtmq_m_uv4si (__inactive, __a, __p);
+ return __builtin_mve_vrev64q_m_uv16qi (vuninitializedq_u8 (), __a, __p);
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtnq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vrev64q_x_u16 (uint16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtnq_m_uv4si (__inactive, __a, __p);
+ return __builtin_mve_vrev64q_m_uv8hi (vuninitializedq_u16 (), __a, __p);
}
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtpq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vrev64q_x_u32 (uint32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vcvtpq_m_uv4si (__inactive, __a, __p);
+ return __builtin_mve_vrev64q_m_uv4si (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+__arm_vrshlq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_from_f_uv4si (__inactive, __a, __p);
+ return __builtin_mve_vrshlq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_n_f16_u16 (float16x8_t __inactive, uint16x8_t __a, const int __imm6, mve_pred16_t __p)
+__arm_vrshlq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_n_to_f_uv8hf (__inactive, __a, __imm6, __p);
+ return __builtin_mve_vrshlq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_n_f16_s16 (float16x8_t __inactive, int16x8_t __a, const int __imm6, mve_pred16_t __p)
+__arm_vrshlq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_n_to_f_sv8hf (__inactive, __a, __imm6, __p);
+ return __builtin_mve_vrshlq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_n_f32_u32 (float32x4_t __inactive, uint32x4_t __a, const int __imm6, mve_pred16_t __p)
+__arm_vrshlq_x_u8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_n_to_f_uv4sf (__inactive, __a, __imm6, __p);
+ return __builtin_mve_vrshlq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_n_f32_s32 (float32x4_t __inactive, int32x4_t __a, const int __imm6, mve_pred16_t __p)
+__arm_vrshlq_x_u16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vcvtq_m_n_to_f_sv4sf (__inactive, __a, __imm6, __p);
+ return __builtin_mve_vrshlq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vabdq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vrshlq_x_u32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vabdq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vrshlq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vabdq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vshllbq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vabdq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vshllbq_m_n_sv16qi (vuninitializedq_s16 (), __a, __imm, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vshllbq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vaddq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vshllbq_m_n_sv8hi (vuninitializedq_s32 (), __a, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vshllbq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vaddq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vshllbq_m_n_uv16qi (vuninitializedq_u16 (), __a, __imm, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p)
+__arm_vshllbq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vaddq_m_n_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vshllbq_m_n_uv8hi (vuninitializedq_u32 (), __a, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p)
+__arm_vshlltq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vaddq_m_n_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vshlltq_m_n_sv16qi (vuninitializedq_s16 (), __a, __imm, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vandq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vshlltq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vandq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vshlltq_m_n_sv8hi (vuninitializedq_s32 (), __a, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vandq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vshlltq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vandq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vshlltq_m_n_uv16qi (vuninitializedq_u16 (), __a, __imm, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vbicq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vshlltq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p)
{
- return __builtin_mve_vbicq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vshlltq_m_n_uv8hi (vuninitializedq_u32 (), __a, __imm, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline int8x16_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vbicq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vshlq_x_s8 (int8x16_t __a, int8x16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vbicq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vshlq_m_sv16qi (vuninitializedq_s8 (), __a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_s16 (int16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_sv8hi (vuninitializedq_s16 (), __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_s32 (int32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_sv4si (vuninitializedq_s32 (), __a, __b, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_u8 (uint8x16_t __a, int8x16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_uv16qi (vuninitializedq_u8 (), __a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_u16 (uint16x8_t __a, int16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_uv8hi (vuninitializedq_u16 (), __a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_u32 (uint32x4_t __a, int32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_uv4si (vuninitializedq_u32 (), __a, __b, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_sv16qi (vuninitializedq_s8 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_sv8hi (vuninitializedq_s16 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_n_s32 (int32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_sv4si (vuninitializedq_s32 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshlq_x_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshlq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_sv16qi (vuninitializedq_s8 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_sv8hi (vuninitializedq_s16 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_x_n_s32 (int32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_sv4si (vuninitializedq_s32 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrshrq_x_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vrshrq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_x_n_s8 (int8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_sv16qi (vuninitializedq_s8 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_x_n_s16 (int16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_sv8hi (vuninitializedq_s16 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_x_n_s32 (int32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_sv4si (vuninitializedq_s32 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_x_n_u8 (uint8x16_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_uv16qi (vuninitializedq_u8 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_x_n_u16 (uint16x8_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_uv8hi (vuninitializedq_u16 (), __a, __imm, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vshrq_x_n_u32 (uint32x4_t __a, const int __imm, mve_pred16_t __p)
+{
+ return __builtin_mve_vshrq_m_n_uv4si (vuninitializedq_u32 (), __a, __imm, __p);
+}
+
+#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vst4q_f16 (float16_t * __addr, float16x8x4_t __value)
+{
+ union { float16x8x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__i = __value;
+ __builtin_mve_vst4qv8hf (__addr, __rv.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vst4q_f32 (float32_t * __addr, float32x4x4_t __value)
+{
+ union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv;
+ __rv.__i = __value;
+ __builtin_mve_vst4qv4sf (__addr, __rv.__o);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndxq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrndxq_fv8hf (__a);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vbrsrq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, int32_t __b, mve_pred16_t __p)
+__arm_vrndxq_f32 (float32x4_t __a)
{
- return __builtin_mve_vbrsrq_m_n_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vrndxq_fv4sf (__a);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vbrsrq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, int32_t __b, mve_pred16_t __p)
+__arm_vrndq_f16 (float16x8_t __a)
{
- return __builtin_mve_vbrsrq_m_n_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vrndq_fv8hf (__a);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcaddq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vrndq_f32 (float32x4_t __a)
{
- return __builtin_mve_vcaddq_rot270_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vrndq_fv4sf (__a);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcaddq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vrndpq_f16 (float16x8_t __a)
{
- return __builtin_mve_vcaddq_rot270_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vrndpq_fv8hf (__a);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcaddq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vrndpq_f32 (float32x4_t __a)
{
- return __builtin_mve_vcaddq_rot90_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vrndpq_fv4sf (__a);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcaddq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vrndnq_f16 (float16x8_t __a)
{
- return __builtin_mve_vcaddq_rot90_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vrndnq_fv8hf (__a);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+__arm_vrndnq_f32 (float32x4_t __a)
{
- return __builtin_mve_vcmlaq_m_fv4sf (__a, __b, __c, __p);
+ return __builtin_mve_vrndnq_fv4sf (__a);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+__arm_vrndmq_f16 (float16x8_t __a)
{
- return __builtin_mve_vcmlaq_m_fv8hf (__a, __b, __c, __p);
+ return __builtin_mve_vrndmq_fv8hf (__a);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot180_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+__arm_vrndmq_f32 (float32x4_t __a)
{
- return __builtin_mve_vcmlaq_rot180_m_fv4sf (__a, __b, __c, __p);
+ return __builtin_mve_vrndmq_fv4sf (__a);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot180_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+__arm_vrndaq_f16 (float16x8_t __a)
{
- return __builtin_mve_vcmlaq_rot180_m_fv8hf (__a, __b, __c, __p);
+ return __builtin_mve_vrndaq_fv8hf (__a);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot270_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+__arm_vrndaq_f32 (float32x4_t __a)
{
- return __builtin_mve_vcmlaq_rot270_m_fv4sf (__a, __b, __c, __p);
+ return __builtin_mve_vrndaq_fv4sf (__a);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot270_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+__arm_vrev64q_f16 (float16x8_t __a)
{
- return __builtin_mve_vcmlaq_rot270_m_fv8hf (__a, __b, __c, __p);
+ return __builtin_mve_vrev64q_fv8hf (__a);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot90_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+__arm_vrev64q_f32 (float32x4_t __a)
{
- return __builtin_mve_vcmlaq_rot90_m_fv4sf (__a, __b, __c, __p);
+ return __builtin_mve_vrev64q_fv4sf (__a);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmlaq_rot90_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+__arm_vnegq_f16 (float16x8_t __a)
{
- return __builtin_mve_vcmlaq_rot90_m_fv8hf (__a, __b, __c, __p);
+ return __builtin_mve_vnegq_fv8hf (__a);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vnegq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vnegq_fv4sf (__a);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vdupq_n_f16 (float16_t __a)
+{
+ return __builtin_mve_vdupq_n_fv8hf (__a);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vdupq_n_f32 (float32_t __a)
+{
+ return __builtin_mve_vdupq_n_fv4sf (__a);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabsq_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vabsq_fv8hf (__a);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabsq_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vabsq_fv4sf (__a);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev32q_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vrev32q_fv8hf (__a);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vcvttq_f32_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvttq_f32_f16v4sf (__a);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtbq_f32_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtbq_f32_f16v4sf (__a);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f16_s16 (int16x8_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_sv8hf (__a);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f32_s32 (int32x4_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_sv4sf (__a);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f16_u16 (uint16x8_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_uv8hf (__a);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_f32_u32 (uint32x4_t __a)
+{
+ return __builtin_mve_vcvtq_to_f_uv4sf (__a);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_s16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtq_from_f_sv8hi (__a);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_s32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtq_from_f_sv4si (__a);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_u16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtq_from_f_uv8hi (__a);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_u32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtq_from_f_uv4si (__a);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtpq_u16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtpq_uv8hi (__a);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtpq_u32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtpq_uv4si (__a);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtnq_u16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtnq_uv8hi (__a);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtmq_u16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtmq_uv8hi (__a);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtmq_u32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtmq_uv4si (__a);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtaq_u16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtaq_uv8hi (__a);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtaq_u32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtaq_uv4si (__a);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtaq_s16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtaq_sv8hi (__a);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtaq_s32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtaq_sv4si (__a);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtnq_s16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtnq_sv8hi (__a);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtnq_s32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtnq_sv4si (__a);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtpq_s16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtpq_sv8hi (__a);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtpq_s32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtpq_sv4si (__a);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtmq_s16_f16 (float16x8_t __a)
+{
+ return __builtin_mve_vcvtmq_sv8hi (__a);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtmq_s32_f32 (float32x4_t __a)
+{
+ return __builtin_mve_vcvtmq_sv4si (__a);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_n_f16 (float16x8_t __a, float16_t __b)
+{
+ return __builtin_mve_vsubq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_n_f32 (float32x4_t __a, float32_t __b)
+{
+ return __builtin_mve_vsubq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_n_f16 (float16x8_t __a, int32_t __b)
+{
+ return __builtin_mve_vbrsrq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_n_f32 (float32x4_t __a, int32_t __b)
+{
+ return __builtin_mve_vbrsrq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_f16_s16 (int16x8_t __a, const int __imm6)
+{
+ return __builtin_mve_vcvtq_n_to_f_sv8hf (__a, __imm6);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_f32_s32 (int32x4_t __a, const int __imm6)
+{
+ return __builtin_mve_vcvtq_n_to_f_sv4sf (__a, __imm6);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_f16_u16 (uint16x8_t __a, const int __imm6)
+{
+ return __builtin_mve_vcvtq_n_to_f_uv8hf (__a, __imm6);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_f32_u32 (uint32x4_t __a, const int __imm6)
+{
+ return __builtin_mve_vcvtq_n_to_f_uv4sf (__a, __imm6);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_f16 (uint64_t __a, uint64_t __b)
+{
+ return __builtin_mve_vcreateq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcreateq_f32 (uint64_t __a, uint64_t __b)
+{
+ return __builtin_mve_vcreateq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_s16_f16 (float16x8_t __a, const int __imm6)
+{
+ return __builtin_mve_vcvtq_n_from_f_sv8hi (__a, __imm6);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_s32_f32 (float32x4_t __a, const int __imm6)
+{
+ return __builtin_mve_vcvtq_n_from_f_sv4si (__a, __imm6);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_u16_f16 (float16x8_t __a, const int __imm6)
+{
+ return __builtin_mve_vcvtq_n_from_f_uv8hi (__a, __imm6);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_n_u32_f32 (float32x4_t __a, const int __imm6)
+{
+ return __builtin_mve_vcvtq_n_from_f_uv4si (__a, __imm6);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpneq_n_f16 (float16x8_t __a, float16_t __b)
+{
+ return __builtin_mve_vcmpneq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpneq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmpneq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpltq_n_f16 (float16x8_t __a, float16_t __b)
+{
+ return __builtin_mve_vcmpltq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpltq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmpltq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpleq_n_f16 (float16x8_t __a, float16_t __b)
+{
+ return __builtin_mve_vcmpleq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpleq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmpleq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgtq_n_f16 (float16x8_t __a, float16_t __b)
+{
+ return __builtin_mve_vcmpgtq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgtq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmpgtq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgeq_n_f16 (float16x8_t __a, float16_t __b)
+{
+ return __builtin_mve_vcmpgeq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgeq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmpgeq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpeqq_n_f16 (float16x8_t __a, float16_t __b)
+{
+ return __builtin_mve_vcmpeqq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpeqq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmpeqq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vsubq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vorrq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vornq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_n_f16 (float16x8_t __a, float16_t __b)
+{
+ return __builtin_mve_vmulq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vmulq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmvq_f16 (float16_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vminnmvq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vminnmq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmavq_f16 (float16_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vminnmavq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmaq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vminnmaq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmvq_f16 (float16_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vmaxnmvq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vmaxnmq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmavq_f16 (float16_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vmaxnmavq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmaq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vmaxnmaq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_veorq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot90_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmulq_rot90_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot270_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmulq_rot270_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot180_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmulq_rot180_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcmulq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcaddq_rot90_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vcaddq_rot270_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vbicq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vandq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_n_f16 (float16x8_t __a, float16_t __b)
+{
+ return __builtin_mve_vaddq_n_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __builtin_mve_vabdq_fv8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpneq_n_f32 (float32x4_t __a, float32_t __b)
+{
+ return __builtin_mve_vcmpneq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpneq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmpneq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpltq_n_f32 (float32x4_t __a, float32_t __b)
+{
+ return __builtin_mve_vcmpltq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpltq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmpltq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpleq_n_f32 (float32x4_t __a, float32_t __b)
+{
+ return __builtin_mve_vcmpleq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpleq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmpleq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgtq_n_f32 (float32x4_t __a, float32_t __b)
+{
+ return __builtin_mve_vcmpgtq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgtq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmpgtq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgeq_n_f32 (float32x4_t __a, float32_t __b)
+{
+ return __builtin_mve_vcmpgeq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgeq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmpgeq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpeqq_n_f32 (float32x4_t __a, float32_t __b)
+{
+ return __builtin_mve_vcmpeqq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpeqq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmpeqq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vsubq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vorrq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vornq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_n_f32 (float32x4_t __a, float32_t __b)
+{
+ return __builtin_mve_vmulq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vmulq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmvq_f32 (float32_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vminnmvq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vminnmq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmavq_f32 (float32_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vminnmavq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmaq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vminnmaq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmvq_f32 (float32_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vmaxnmvq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vmaxnmq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmavq_f32 (float32_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vmaxnmavq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmaq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vmaxnmaq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_veorq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot90_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmulq_rot90_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot270_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmulq_rot270_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot180_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmulq_rot180_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcmulq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcaddq_rot90_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcaddq_rot270_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vbicq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vandq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_n_f32 (float32x4_t __a, float32_t __b)
+{
+ return __builtin_mve_vaddq_n_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vabdq_fv4sf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvttq_f16_f32 (float16x8_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcvttq_f16_f32v8hf (__a, __b);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtbq_f16_f32 (float16x8_t __a, float32x4_t __b)
+{
+ return __builtin_mve_vcvtbq_f16_f32v8hf (__a, __b);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpeqq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpeqq_m_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpeqq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpeqq_m_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtaq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtaq_m_sv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtaq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtaq_m_uv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtaq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtaq_m_sv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtaq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtaq_m_uv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_f16_s16 (float16x8_t __inactive, int16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_to_f_sv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_f16_u16 (float16x8_t __inactive, uint16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_to_f_uv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_f32_s32 (float32x4_t __inactive, int32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_to_f_sv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_f32_u32 (float32x4_t __inactive, uint32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_to_f_uv4sf (__inactive, __a, __p);
+}
+
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtbq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtbq_m_f16_f32v8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtbq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtbq_m_f32_f16v4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvttq_m_f16_f32 (float16x8_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvttq_m_f16_f32v8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvttq_m_f32_f16 (float32x4_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvttq_m_f32_f16v4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev32q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrev32q_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+{
+ return __builtin_mve_vcmlaq_fv8hf (__a, __b, __c);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot180_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+{
+ return __builtin_mve_vcmlaq_rot180_fv8hf (__a, __b, __c);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot270_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+{
+ return __builtin_mve_vcmlaq_rot270_fv8hf (__a, __b, __c);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot90_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+{
+ return __builtin_mve_vcmlaq_rot90_fv8hf (__a, __b, __c);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmaq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+{
+ return __builtin_mve_vfmaq_fv8hf (__a, __b, __c);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmaq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
+{
+ return __builtin_mve_vfmaq_n_fv8hf (__a, __b, __c);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmasq_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c)
+{
+ return __builtin_mve_vfmasq_n_fv8hf (__a, __b, __c);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmsq_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c)
+{
+ return __builtin_mve_vfmsq_fv8hf (__a, __b, __c);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabsq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vabsq_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtmq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtmq_m_sv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtnq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtnq_m_sv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtpq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtpq_m_sv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_s16_f16 (int16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_from_f_sv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vdupq_m_n_f16 (float16x8_t __inactive, float16_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vdupq_m_n_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxnmaq_m_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline float16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxnmavq_p_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline float16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxnmvq_p_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmaq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminnmaq_m_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline float16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmavq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminnmavq_p_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline float16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmvq_p_f16 (float16_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminnmvq_p_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vnegq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vnegq_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vpselq_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vpselq_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev64q_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrev64q_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndaq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndaq_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndmq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndmq_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndnq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndnq_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndpq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndpq_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndq_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndxq_m_f16 (float16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndxq_m_fv8hf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpeqq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpeqq_m_n_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgeq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpgeq_m_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgeq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpgeq_m_n_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgtq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpgtq_m_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgtq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpgtq_m_n_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpleq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpleq_m_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpleq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpleq_m_n_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpltq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpltq_m_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpltq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpltq_m_n_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpneq_m_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpneq_m_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpneq_m_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpneq_m_n_fv8hf (__a, __b, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtmq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtmq_m_uv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtnq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtnq_m_uv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtpq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtpq_m_uv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_u16_f16 (uint16x8_t __inactive, float16x8_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_from_f_uv8hi (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+{
+ return __builtin_mve_vcmlaq_fv4sf (__a, __b, __c);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot180_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+{
+ return __builtin_mve_vcmlaq_rot180_fv4sf (__a, __b, __c);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot270_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+{
+ return __builtin_mve_vcmlaq_rot270_fv4sf (__a, __b, __c);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot90_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+{
+ return __builtin_mve_vcmlaq_rot90_fv4sf (__a, __b, __c);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmaq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+{
+ return __builtin_mve_vfmaq_fv4sf (__a, __b, __c);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+{
+ return __builtin_mve_vfmaq_n_fv4sf (__a, __b, __c);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmasq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
+{
+ return __builtin_mve_vfmasq_n_fv4sf (__a, __b, __c);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmsq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+{
+ return __builtin_mve_vfmsq_fv4sf (__a, __b, __c);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabsq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vabsq_m_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtmq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtmq_m_sv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtnq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtnq_m_sv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtpq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtpq_m_sv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_s32_f32 (int32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_from_f_sv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vdupq_m_n_f32 (float32x4_t __inactive, float32_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vdupq_m_n_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxnmaq_m_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline float32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxnmavq_p_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline float32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxnmvq_p_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmaq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminnmaq_m_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline float32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmavq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminnmavq_p_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline float32_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmvq_p_f32 (float32_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminnmvq_p_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vnegq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vnegq_m_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vpselq_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vpselq_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrev64q_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrev64q_m_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndaq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndaq_m_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndmq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndmq_m_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndnq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndnq_m_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndpq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndpq_m_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndq_m_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vrndxq_m_f32 (float32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vrndxq_m_fv4sf (__inactive, __a, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpeqq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpeqq_m_n_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgeq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpgeq_m_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgeq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpgeq_m_n_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgtq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpgtq_m_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpgtq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpgtq_m_n_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpleq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpleq_m_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpleq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpleq_m_n_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpltq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpltq_m_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpltq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpltq_m_n_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpneq_m_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpneq_m_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmpneq_m_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmpneq_m_n_fv4sf (__a, __b, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtmq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtmq_m_uv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtnq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtnq_m_uv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtpq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtpq_m_uv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_u32_f32 (uint32x4_t __inactive, float32x4_t __a, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_from_f_uv4si (__inactive, __a, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_n_f16_u16 (float16x8_t __inactive, uint16x8_t __a, const int __imm6, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_n_to_f_uv8hf (__inactive, __a, __imm6, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_n_f16_s16 (float16x8_t __inactive, int16x8_t __a, const int __imm6, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_n_to_f_sv8hf (__inactive, __a, __imm6, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_n_f32_u32 (float32x4_t __inactive, uint32x4_t __a, const int __imm6, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_n_to_f_uv4sf (__inactive, __a, __imm6, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_n_f32_s32 (float32x4_t __inactive, int32x4_t __a, const int __imm6, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_n_to_f_sv4sf (__inactive, __a, __imm6, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vabdq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vabdq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vabdq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_n_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vaddq_m_n_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vandq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vandq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vandq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbicq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbicq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbicq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbrsrq_m_n_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vbrsrq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, int32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vbrsrq_m_n_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot270_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot270_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot90_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcaddq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcaddq_rot90_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmlaq_m_fv4sf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmlaq_m_fv8hf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot180_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmlaq_rot180_m_fv4sf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot180_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmlaq_rot180_m_fv8hf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot270_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmlaq_rot270_m_fv4sf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot270_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmlaq_rot270_m_fv8hf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot90_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmlaq_rot90_m_fv4sf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmlaq_rot90_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmlaq_rot90_m_fv8hf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmulq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmulq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot180_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmulq_rot180_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot180_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmulq_rot180_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmulq_rot270_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmulq_rot270_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmulq_rot90_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcmulq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vcmulq_rot90_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_n_s32_f32 (int32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_n_from_f_sv4si (__inactive, __a, __imm6, __p);
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_n_s16_f16 (int16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_n_from_f_sv8hi (__inactive, __a, __imm6, __p);
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_n_u32_f32 (uint32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_n_from_f_uv4si (__inactive, __a, __imm6, __p);
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vcvtq_m_n_u16_f16 (uint16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p)
+{
+ return __builtin_mve_vcvtq_m_n_from_f_uv8hi (__inactive, __a, __imm6, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_veorq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_veorq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_veorq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vfmaq_m_fv4sf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vfmaq_m_fv8hf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmaq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vfmaq_m_n_fv4sf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmaq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vfmaq_m_n_fv8hf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmasq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vfmasq_m_n_fv4sf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmasq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vfmasq_m_n_fv8hf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmsq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vfmsq_m_fv4sf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vfmsq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+{
+ return __builtin_mve_vfmsq_m_fv8hf (__a, __b, __c, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxnmq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmaxnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmaxnmq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminnmq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vminnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vminnmq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_n_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vmulq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vmulq_m_n_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vornq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vornq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vornq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vorrq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vorrq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vorrq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_n_fv4sf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p)
+{
+ return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_f32 (float32_t const * __base)
+{
+ return __builtin_mve_vld1q_fv4sf((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vld1q_f16 (float16_t const * __base)
+{
+ return __builtin_mve_vld1q_fv8hf((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_f32 (float32_t const * __base)
+{
+ return __builtin_mve_vldrwq_fv4sf((__builtin_neon_si *) __base);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_z_f32 (float32_t const * __base, mve_pred16_t __p)
+{
+ return __builtin_mve_vldrwq_z_fv4sf((__builtin_neon_si *) __base, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_z_f16 (float16_t const * __base, mve_pred16_t __p)
+{
+ return __builtin_mve_vldrhq_z_fv8hf((__builtin_neon_hi *) __base, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_f16 (float16_t const * __base)
+{
+ return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_f16 (float16_t const * __base, uint16x8_t __offset)
+{
+ return __builtin_mve_vldrhq_gather_offset_fv8hf((__builtin_neon_hi *) __base, __offset);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+ return __builtin_mve_vldrhq_gather_offset_z_fv8hf((__builtin_neon_hi *) __base, __offset, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_f16 (float16_t const * __base, uint16x8_t __offset)
+{
+ return __builtin_mve_vldrhq_gather_shifted_offset_fv8hf (__base, __offset);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrhq_gather_shifted_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+{
+ return __builtin_mve_vldrhq_gather_shifted_offset_z_fv8hf (__base, __offset, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_base_f32 (uint32x4_t __addr, const int __offset)
+{
+ return __builtin_mve_vldrwq_gather_base_fv4sf (__addr, __offset);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_base_z_f32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p)
+{
+ return __builtin_mve_vldrwq_gather_base_z_fv4sf (__addr, __offset, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_offset_f32 (float32_t const * __base, uint32x4_t __offset)
+{
+ return __builtin_mve_vldrwq_gather_offset_fv4sf((__builtin_neon_si *) __base, __offset);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+ return __builtin_mve_vldrwq_gather_offset_z_fv4sf((__builtin_neon_si *) __base, __offset, __p);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_shifted_offset_f32 (float32_t const * __base, uint32x4_t __offset)
+{
+ return __builtin_mve_vldrwq_gather_shifted_offset_fv4sf (__base, __offset);
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vldrwq_gather_shifted_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+{
+ return __builtin_mve_vldrwq_gather_shifted_offset_z_fv4sf (__base, __offset, __p);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrwq_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t __p)
+{
+ __builtin_mve_vstrwq_p_fv4sf (__addr, __value, __p);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrwq_f32 (float32_t * __addr, float32x4_t __value)
+{
+ __builtin_mve_vstrwq_fv4sf (__addr, __value);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vst1q_f32 (float32_t * __addr, float32x4_t __value)
+{
+ __builtin_mve_vst1q_fv4sf (__addr, __value);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vst1q_f16 (float16_t * __addr, float16x8_t __value)
+{
+ __builtin_mve_vst1q_fv8hf (__addr, __value);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrhq_f16 (float16_t * __addr, float16x8_t __value)
+{
+ __builtin_mve_vstrhq_fv8hf (__addr, __value);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrhq_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p)
+{
+ __builtin_mve_vstrhq_p_fv8hf (__addr, __value, __p);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrhq_scatter_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value)
+{
+ __builtin_mve_vstrhq_scatter_offset_fv8hf (__base, __offset, __value);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrhq_scatter_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p)
+{
+ __builtin_mve_vstrhq_scatter_offset_p_fv8hf (__base, __offset, __value, __p);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrhq_scatter_shifted_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value)
+{
+ __builtin_mve_vstrhq_scatter_shifted_offset_fv8hf (__base, __offset, __value);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrhq_scatter_shifted_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p)
+{
+ __builtin_mve_vstrhq_scatter_shifted_offset_p_fv8hf (__base, __offset, __value, __p);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrwq_scatter_base_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value)
+{
+ __builtin_mve_vstrwq_scatter_base_fv4sf (__addr, __offset, __value);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrwq_scatter_base_p_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value, mve_pred16_t __p)
+{
+ __builtin_mve_vstrwq_scatter_base_p_fv4sf (__addr, __offset, __value, __p);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrwq_scatter_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value)
+{
+ __builtin_mve_vstrwq_scatter_offset_fv4sf (__base, __offset, __value);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrwq_scatter_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p)
+{
+ __builtin_mve_vstrwq_scatter_offset_p_fv4sf (__base, __offset, __value, __p);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrwq_scatter_shifted_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value)
+{
+ __builtin_mve_vstrwq_scatter_shifted_offset_fv4sf (__base, __offset, __value);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vstrwq_scatter_shifted_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p)
+{
+ __builtin_mve_vstrwq_scatter_shifted_offset_p_fv4sf (__base, __offset, __value, __p);
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_f16 (float16x8_t __a, float16x8_t __b)
+{
+ return __a + __b;
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vaddq_f32 (float32x4_t __a, float32x4_t __b)
+{
+ return __a + __b;
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_f16 (void)
+{
+ float16x8_t __uninit;
+ __asm__ ("": "=w" (__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline float32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vuninitializedq_f32 (void)
+{
+ float32x4_t __uninit;
+ __asm__ ("": "=w" (__uninit));
+ return __uninit;
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_s32_f16 (float16x8_t __a)
+{
+ return (int32x4_t) __a;
+}
+
+__extension__ extern __inline int32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_s32_f32 (float32x4_t __a)
+{
+ return (int32x4_t) __a;
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_s16_f16 (float16x8_t __a)
+{
+ return (int16x8_t) __a;
+}
+
+__extension__ extern __inline int16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_s16_f32 (float32x4_t __a)
+{
+ return (int16x8_t) __a;
+}
+
+__extension__ extern __inline int64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_s64_f16 (float16x8_t __a)
+{
+ return (int64x2_t) __a;
+}
+
+__extension__ extern __inline int64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_s64_f32 (float32x4_t __a)
+{
+ return (int64x2_t) __a;
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_s8_f16 (float16x8_t __a)
+{
+ return (int8x16_t) __a;
+}
+
+__extension__ extern __inline int8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_s8_f32 (float32x4_t __a)
+{
+ return (int8x16_t) __a;
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_u16_f16 (float16x8_t __a)
+{
+ return (uint16x8_t) __a;
+}
+
+__extension__ extern __inline uint16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_u16_f32 (float32x4_t __a)
+{
+ return (uint16x8_t) __a;
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_u32_f16 (float16x8_t __a)
+{
+ return (uint32x4_t) __a;
+}
+
+__extension__ extern __inline uint32x4_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_u32_f32 (float32x4_t __a)
+{
+ return (uint32x4_t) __a;
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_u64_f16 (float16x8_t __a)
+{
+ return (uint64x2_t) __a;
+}
+
+__extension__ extern __inline uint64x2_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_u64_f32 (float32x4_t __a)
+{
+ return (uint64x2_t) __a;
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_u8_f16 (float16x8_t __a)
+{
+ return (uint8x16_t) __a;
+}
+
+__extension__ extern __inline uint8x16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_u8_f32 (float32x4_t __a)
+{
+ return (uint8x16_t) __a;
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_f16_f32 (float32x4_t __a)
+{
+ return (float16x8_t) __a;
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_f16_s16 (int16x8_t __a)
+{
+ return (float16x8_t) __a;
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_f16_s32 (int32x4_t __a)
+{
+ return (float16x8_t) __a;
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_f16_s64 (int64x2_t __a)
+{
+ return (float16x8_t) __a;
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_f16_s8 (int8x16_t __a)
+{
+ return (float16x8_t) __a;
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_f16_u16 (uint16x8_t __a)
+{
+ return (float16x8_t) __a;
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_f16_u32 (uint32x4_t __a)
+{
+ return (float16x8_t) __a;
+}
+
+__extension__ extern __inline float16x8_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vreinterpretq_f16_u64 (uint64x2_t __a)
{
- return __builtin_mve_vcmulq_m_fv4sf (__inactive, __a, __b, __p);
+ return (float16x8_t) __a;
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vreinterpretq_f16_u8 (uint8x16_t __a)
{
- return __builtin_mve_vcmulq_m_fv8hf (__inactive, __a, __b, __p);
+ return (float16x8_t) __a;
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot180_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vreinterpretq_f32_f16 (float16x8_t __a)
{
- return __builtin_mve_vcmulq_rot180_m_fv4sf (__inactive, __a, __b, __p);
+ return (float32x4_t) __a;
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot180_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vreinterpretq_f32_s16 (int16x8_t __a)
{
- return __builtin_mve_vcmulq_rot180_m_fv8hf (__inactive, __a, __b, __p);
+ return (float32x4_t) __a;
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot270_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vreinterpretq_f32_s32 (int32x4_t __a)
{
- return __builtin_mve_vcmulq_rot270_m_fv4sf (__inactive, __a, __b, __p);
+ return (float32x4_t) __a;
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot270_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vreinterpretq_f32_s64 (int64x2_t __a)
{
- return __builtin_mve_vcmulq_rot270_m_fv8hf (__inactive, __a, __b, __p);
+ return (float32x4_t) __a;
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot90_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vreinterpretq_f32_s8 (int8x16_t __a)
{
- return __builtin_mve_vcmulq_rot90_m_fv4sf (__inactive, __a, __b, __p);
+ return (float32x4_t) __a;
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcmulq_rot90_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vreinterpretq_f32_u16 (uint16x8_t __a)
{
- return __builtin_mve_vcmulq_rot90_m_fv8hf (__inactive, __a, __b, __p);
+ return (float32x4_t) __a;
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_n_s32_f32 (int32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p)
+__arm_vreinterpretq_f32_u32 (uint32x4_t __a)
{
- return __builtin_mve_vcvtq_m_n_from_f_sv4si (__inactive, __a, __imm6, __p);
+ return (float32x4_t) __a;
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_n_s16_f16 (int16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p)
+__arm_vreinterpretq_f32_u64 (uint64x2_t __a)
{
- return __builtin_mve_vcvtq_m_n_from_f_sv8hi (__inactive, __a, __imm6, __p);
+ return (float32x4_t) __a;
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_n_u32_f32 (uint32x4_t __inactive, float32x4_t __a, const int __imm6, mve_pred16_t __p)
+__arm_vreinterpretq_f32_u8 (uint8x16_t __a)
{
- return __builtin_mve_vcvtq_m_n_from_f_uv4si (__inactive, __a, __imm6, __p);
+ return (float32x4_t) __a;
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vcvtq_m_n_u16_f16 (uint16x8_t __inactive, float16x8_t __a, const int __imm6, mve_pred16_t __p)
+__arm_vldrwq_gather_base_wb_f32 (uint32x4_t * __addr, const int __offset)
{
- return __builtin_mve_vcvtq_m_n_from_f_uv8hi (__inactive, __a, __imm6, __p);
+ float32x4_t
+ result = __builtin_mve_vldrwq_gather_base_wb_fv4sf (*__addr, __offset);
+ __addr += __offset;
+ return result;
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_veorq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vldrwq_gather_base_wb_z_f32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p)
{
- return __builtin_mve_veorq_m_fv4sf (__inactive, __a, __b, __p);
+ float32x4_t
+ result = __builtin_mve_vldrwq_gather_base_wb_z_fv4sf (*__addr, __offset, __p);
+ __addr += __offset;
+ return result;
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_veorq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vstrwq_scatter_base_wb_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value)
{
- return __builtin_mve_veorq_m_fv8hf (__inactive, __a, __b, __p);
+ __builtin_mve_vstrwq_scatter_base_wb_fv4sf (*__addr, __offset, __value);
+ __builtin_mve_vstrwq_scatter_base_wb_add_fv4sf (*__addr, __offset, *__addr);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmaq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+__arm_vstrwq_scatter_base_wb_p_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value, mve_pred16_t __p)
{
- return __builtin_mve_vfmaq_m_fv4sf (__a, __b, __c, __p);
+ __builtin_mve_vstrwq_scatter_base_wb_p_fv4sf (*__addr, __offset, __value, __p);
+ __builtin_mve_vstrwq_scatter_base_wb_p_add_fv4sf (*__addr, __offset, *__addr, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmaq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+__arm_vdupq_x_n_f16 (float16_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vfmaq_m_fv8hf (__a, __b, __c, __p);
+ return __builtin_mve_vdupq_m_n_fv8hf (vuninitializedq_f16 (), __a, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmaq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p)
+__arm_vdupq_x_n_f32 (float32_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vfmaq_m_n_fv4sf (__a, __b, __c, __p);
+ return __builtin_mve_vdupq_m_n_fv4sf (vuninitializedq_f32 (), __a, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmaq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p)
+__arm_vminnmq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vfmaq_m_n_fv8hf (__a, __b, __c, __p);
+ return __builtin_mve_vminnmq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmasq_m_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c, mve_pred16_t __p)
+__arm_vminnmq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vfmasq_m_n_fv4sf (__a, __b, __c, __p);
+ return __builtin_mve_vminnmq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmasq_m_n_f16 (float16x8_t __a, float16x8_t __b, float16_t __c, mve_pred16_t __p)
+__arm_vmaxnmq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vfmasq_m_n_fv8hf (__a, __b, __c, __p);
+ return __builtin_mve_vmaxnmq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmsq_m_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c, mve_pred16_t __p)
+__arm_vmaxnmq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vfmsq_m_fv4sf (__a, __b, __c, __p);
+ return __builtin_mve_vmaxnmq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vfmsq_m_f16 (float16x8_t __a, float16x8_t __b, float16x8_t __c, mve_pred16_t __p)
+__arm_vabdq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vfmsq_m_fv8hf (__a, __b, __c, __p);
+ return __builtin_mve_vabdq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vabdq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vabdq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmaxnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vabsq_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vmaxnmq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vabsq_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vabsq_x_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vminnmq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vabsq_m_fv4sf (vuninitializedq_f32 (), __a, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vminnmq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vaddq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vminnmq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vaddq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmulq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vaddq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmulq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vaddq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmulq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vaddq_x_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmulq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vaddq_m_n_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmulq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p)
+__arm_vaddq_x_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vmulq_m_n_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vaddq_m_n_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vmulq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p)
+__arm_vnegq_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vmulq_m_n_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vnegq_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vornq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vnegq_x_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vornq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vnegq_m_fv4sf (vuninitializedq_f32 (), __a, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vornq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vmulq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vornq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vmulq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vorrq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vmulq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vorrq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vmulq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vorrq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vmulq_x_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vorrq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vmulq_m_n_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vsubq_m_f32 (float32x4_t __inactive, float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
+__arm_vmulq_x_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vsubq_m_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vmulq_m_n_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vsubq_m_f16 (float16x8_t __inactive, float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
+__arm_vsubq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vsubq_m_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vsubq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vsubq_m_n_f32 (float32x4_t __inactive, float32x4_t __a, float32_t __b, mve_pred16_t __p)
+__arm_vsubq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vsubq_m_n_fv4sf (__inactive, __a, __b, __p);
+ return __builtin_mve_vsubq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vsubq_m_n_f16 (float16x8_t __inactive, float16x8_t __a, float16_t __b, mve_pred16_t __p)
+__arm_vsubq_x_n_f16 (float16x8_t __a, float16_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vsubq_m_n_fv8hf (__inactive, __a, __b, __p);
+ return __builtin_mve_vsubq_m_n_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vld1q_f32 (float32_t const * __base)
+__arm_vsubq_x_n_f32 (float32x4_t __a, float32_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vld1q_fv4sf((__builtin_neon_si *) __base);
+ return __builtin_mve_vsubq_m_n_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vld1q_f16 (float16_t const * __base)
+__arm_vcaddq_rot90_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vld1q_fv8hf((__builtin_neon_hi *) __base);
+ return __builtin_mve_vcaddq_rot90_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_f32 (float32_t const * __base)
+__arm_vcaddq_rot90_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrwq_fv4sf((__builtin_neon_si *) __base);
+ return __builtin_mve_vcaddq_rot90_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_z_f32 (float32_t const * __base, mve_pred16_t __p)
+__arm_vcaddq_rot270_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrwq_z_fv4sf((__builtin_neon_si *) __base, __p);
+ return __builtin_mve_vcaddq_rot270_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrhq_z_f16 (float16_t const * __base, mve_pred16_t __p)
+__arm_vcaddq_rot270_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrhq_z_fv8hf((__builtin_neon_hi *) __base, __p);
+ return __builtin_mve_vcaddq_rot270_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrhq_f16 (float16_t const * __base)
+__arm_vcmulq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrhq_fv8hf((__builtin_neon_hi *) __base);
+ return __builtin_mve_vcmulq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrhq_gather_offset_f16 (float16_t const * __base, uint16x8_t __offset)
+__arm_vcmulq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrhq_gather_offset_fv8hf((__builtin_neon_hi *) __base, __offset);
+ return __builtin_mve_vcmulq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrhq_gather_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+__arm_vcmulq_rot90_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrhq_gather_offset_z_fv8hf((__builtin_neon_hi *) __base, __offset, __p);
+ return __builtin_mve_vcmulq_rot90_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrhq_gather_shifted_offset_f16 (float16_t const * __base, uint16x8_t __offset)
+__arm_vcmulq_rot90_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrhq_gather_shifted_offset_fv8hf (__base, __offset);
+ return __builtin_mve_vcmulq_rot90_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrhq_gather_shifted_offset_z_f16 (float16_t const * __base, uint16x8_t __offset, mve_pred16_t __p)
+__arm_vcmulq_rot180_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrhq_gather_shifted_offset_z_fv8hf (__base, __offset, __p);
+ return __builtin_mve_vcmulq_rot180_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_gather_base_f32 (uint32x4_t __addr, const int __offset)
+__arm_vcmulq_rot180_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrwq_gather_base_fv4sf (__addr, __offset);
+ return __builtin_mve_vcmulq_rot180_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_gather_base_z_f32 (uint32x4_t __addr, const int __offset, mve_pred16_t __p)
+__arm_vcmulq_rot270_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrwq_gather_base_z_fv4sf (__addr, __offset, __p);
+ return __builtin_mve_vcmulq_rot270_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_gather_offset_f32 (float32_t const * __base, uint32x4_t __offset)
+__arm_vcmulq_rot270_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return __builtin_mve_vldrwq_gather_offset_fv4sf((__builtin_neon_si *) __base, __offset);
+ return __builtin_mve_vcmulq_rot270_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_gather_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+__arm_vcvtaq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vldrwq_gather_offset_z_fv4sf((__builtin_neon_si *) __base, __offset, __p);
+ return __builtin_mve_vcvtaq_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_gather_shifted_offset_f32 (float32_t const * __base, uint32x4_t __offset)
+__arm_vcvtaq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vldrwq_gather_shifted_offset_fv4sf (__base, __offset);
+ return __builtin_mve_vcvtaq_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_gather_shifted_offset_z_f32 (float32_t const * __base, uint32x4_t __offset, mve_pred16_t __p)
+__arm_vcvtaq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return __builtin_mve_vldrwq_gather_shifted_offset_z_fv4sf (__base, __offset, __p);
+ return __builtin_mve_vcvtaq_m_uv8hi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_p_f32 (float32_t * __addr, float32x4_t __value, mve_pred16_t __p)
+__arm_vcvtaq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_p_fv4sf (__addr, __value, __p);
+ return __builtin_mve_vcvtaq_m_uv4si (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_f32 (float32_t * __addr, float32x4_t __value)
+__arm_vcvtnq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_fv4sf (__addr, __value);
+ return __builtin_mve_vcvtnq_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vst1q_f32 (float32_t * __addr, float32x4_t __value)
+__arm_vcvtnq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- __builtin_mve_vst1q_fv4sf (__addr, __value);
+ return __builtin_mve_vcvtnq_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vst1q_f16 (float16_t * __addr, float16x8_t __value)
+__arm_vcvtnq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vst1q_fv8hf (__addr, __value);
+ return __builtin_mve_vcvtnq_m_uv8hi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrhq_f16 (float16_t * __addr, float16x8_t __value)
+__arm_vcvtnq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrhq_fv8hf (__addr, __value);
+ return __builtin_mve_vcvtnq_m_uv4si (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrhq_p_f16 (float16_t * __addr, float16x8_t __value, mve_pred16_t __p)
+__arm_vcvtpq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrhq_p_fv8hf (__addr, __value, __p);
+ return __builtin_mve_vcvtpq_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrhq_scatter_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value)
+__arm_vcvtpq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrhq_scatter_offset_fv8hf (__base, __offset, __value);
+ return __builtin_mve_vcvtpq_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrhq_scatter_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p)
+__arm_vcvtpq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrhq_scatter_offset_p_fv8hf (__base, __offset, __value, __p);
+ return __builtin_mve_vcvtpq_m_uv8hi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrhq_scatter_shifted_offset_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value)
+__arm_vcvtpq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrhq_scatter_shifted_offset_fv8hf (__base, __offset, __value);
+ return __builtin_mve_vcvtpq_m_uv4si (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrhq_scatter_shifted_offset_p_f16 (float16_t * __base, uint16x8_t __offset, float16x8_t __value, mve_pred16_t __p)
+__arm_vcvtmq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrhq_scatter_shifted_offset_p_fv8hf (__base, __offset, __value, __p);
+ return __builtin_mve_vcvtmq_m_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_scatter_base_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value)
+__arm_vcvtmq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_scatter_base_fv4sf (__addr, __offset, __value);
+ return __builtin_mve_vcvtmq_m_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_scatter_base_p_f32 (uint32x4_t __addr, const int __offset, float32x4_t __value, mve_pred16_t __p)
+__arm_vcvtmq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_scatter_base_p_fv4sf (__addr, __offset, __value, __p);
+ return __builtin_mve_vcvtmq_m_uv8hi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_scatter_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value)
+__arm_vcvtmq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_scatter_offset_fv4sf (__base, __offset, __value);
+ return __builtin_mve_vcvtmq_m_uv4si (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_scatter_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p)
+__arm_vcvtbq_x_f32_f16 (float16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_scatter_offset_p_fv4sf (__base, __offset, __value, __p);
+ return __builtin_mve_vcvtbq_m_f32_f16v4sf (vuninitializedq_f32 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_scatter_shifted_offset_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value)
+__arm_vcvttq_x_f32_f16 (float16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_scatter_shifted_offset_fv4sf (__base, __offset, __value);
+ return __builtin_mve_vcvttq_m_f32_f16v4sf (vuninitializedq_f32 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_scatter_shifted_offset_p_f32 (float32_t * __base, uint32x4_t __offset, float32x4_t __value, mve_pred16_t __p)
+__arm_vcvtq_x_f16_u16 (uint16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_scatter_shifted_offset_p_fv4sf (__base, __offset, __value, __p);
+ return __builtin_mve_vcvtq_m_to_f_uv8hf (vuninitializedq_f16 (), __a, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_f16 (float16x8_t __a, float16x8_t __b)
+__arm_vcvtq_x_f16_s16 (int16x8_t __a, mve_pred16_t __p)
{
- return __a + __b;
+ return __builtin_mve_vcvtq_m_to_f_sv8hf (vuninitializedq_f16 (), __a, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vaddq_f32 (float32x4_t __a, float32x4_t __b)
+__arm_vcvtq_x_f32_s32 (int32x4_t __a, mve_pred16_t __p)
{
- return __a + __b;
+ return __builtin_mve_vcvtq_m_to_f_sv4sf (vuninitializedq_f32 (), __a, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_f16 (void)
+__arm_vcvtq_x_f32_u32 (uint32x4_t __a, mve_pred16_t __p)
{
- float16x8_t __uninit;
- __asm__ ("": "=w" (__uninit));
- return __uninit;
+ return __builtin_mve_vcvtq_m_to_f_uv4sf (vuninitializedq_f32 (), __a, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_f32 (void)
+__arm_vcvtq_x_n_f16_s16 (int16x8_t __a, const int __imm6, mve_pred16_t __p)
{
- float32x4_t __uninit;
- __asm__ ("": "=w" (__uninit));
- return __uninit;
+ return __builtin_mve_vcvtq_m_n_to_f_sv8hf (vuninitializedq_f16 (), __a, __imm6, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32_f16 (float16x8_t __a)
+__arm_vcvtq_x_n_f16_u16 (uint16x8_t __a, const int __imm6, mve_pred16_t __p)
{
- return (int32x4_t) __a;
+ return __builtin_mve_vcvtq_m_n_to_f_uv8hf (vuninitializedq_f16 (), __a, __imm6, __p);
}
-__extension__ extern __inline int32x4_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32_f32 (float32x4_t __a)
+__arm_vcvtq_x_n_f32_s32 (int32x4_t __a, const int __imm6, mve_pred16_t __p)
{
- return (int32x4_t) __a;
+ return __builtin_mve_vcvtq_m_n_to_f_sv4sf (vuninitializedq_f32 (), __a, __imm6, __p);
}
-__extension__ extern __inline int16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16_f16 (float16x8_t __a)
+__arm_vcvtq_x_n_f32_u32 (uint32x4_t __a, const int __imm6, mve_pred16_t __p)
{
- return (int16x8_t) __a;
+ return __builtin_mve_vcvtq_m_n_to_f_uv4sf (vuninitializedq_f32 (), __a, __imm6, __p);
}
__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16_f32 (float32x4_t __a)
+__arm_vcvtq_x_s16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return (int16x8_t) __a;
+ return __builtin_mve_vcvtq_m_from_f_sv8hi (vuninitializedq_s16 (), __a, __p);
}
-__extension__ extern __inline int64x2_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64_f16 (float16x8_t __a)
+__arm_vcvtq_x_s32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return (int64x2_t) __a;
+ return __builtin_mve_vcvtq_m_from_f_sv4si (vuninitializedq_s32 (), __a, __p);
}
-__extension__ extern __inline int64x2_t
+__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64_f32 (float32x4_t __a)
+__arm_vcvtq_x_u16_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return (int64x2_t) __a;
+ return __builtin_mve_vcvtq_m_from_f_uv8hi (vuninitializedq_u16 (), __a, __p);
}
-__extension__ extern __inline int8x16_t
+__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8_f16 (float16x8_t __a)
+__arm_vcvtq_x_u32_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return (int8x16_t) __a;
+ return __builtin_mve_vcvtq_m_from_f_uv4si (vuninitializedq_u32 (), __a, __p);
}
-__extension__ extern __inline int8x16_t
+__extension__ extern __inline int16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8_f32 (float32x4_t __a)
+__arm_vcvtq_x_n_s16_f16 (float16x8_t __a, const int __imm6, mve_pred16_t __p)
{
- return (int8x16_t) __a;
+ return __builtin_mve_vcvtq_m_n_from_f_sv8hi (vuninitializedq_s16 (), __a, __imm6, __p);
}
-__extension__ extern __inline uint16x8_t
+__extension__ extern __inline int32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16_f16 (float16x8_t __a)
+__arm_vcvtq_x_n_s32_f32 (float32x4_t __a, const int __imm6, mve_pred16_t __p)
{
- return (uint16x8_t) __a;
+ return __builtin_mve_vcvtq_m_n_from_f_sv4si (vuninitializedq_s32 (), __a, __imm6, __p);
}
__extension__ extern __inline uint16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16_f32 (float32x4_t __a)
+__arm_vcvtq_x_n_u16_f16 (float16x8_t __a, const int __imm6, mve_pred16_t __p)
{
- return (uint16x8_t) __a;
+ return __builtin_mve_vcvtq_m_n_from_f_uv8hi (vuninitializedq_u16 (), __a, __imm6, __p);
}
__extension__ extern __inline uint32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32_f16 (float16x8_t __a)
+__arm_vcvtq_x_n_u32_f32 (float32x4_t __a, const int __imm6, mve_pred16_t __p)
{
- return (uint32x4_t) __a;
+ return __builtin_mve_vcvtq_m_n_from_f_uv4si (vuninitializedq_u32 (), __a, __imm6, __p);
}
-__extension__ extern __inline uint32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32_f32 (float32x4_t __a)
+__arm_vrndq_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return (uint32x4_t) __a;
+ return __builtin_mve_vrndq_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
-__extension__ extern __inline uint64x2_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64_f16 (float16x8_t __a)
+__arm_vrndq_x_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return (uint64x2_t) __a;
+ return __builtin_mve_vrndq_m_fv4sf (vuninitializedq_f32 (), __a, __p);
}
-__extension__ extern __inline uint64x2_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64_f32 (float32x4_t __a)
+__arm_vrndnq_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return (uint64x2_t) __a;
+ return __builtin_mve_vrndnq_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
-__extension__ extern __inline uint8x16_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8_f16 (float16x8_t __a)
+__arm_vrndnq_x_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return (uint8x16_t) __a;
+ return __builtin_mve_vrndnq_m_fv4sf (vuninitializedq_f32 (), __a, __p);
}
-__extension__ extern __inline uint8x16_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8_f32 (float32x4_t __a)
+__arm_vrndmq_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return (uint8x16_t) __a;
+ return __builtin_mve_vrndmq_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_f32 (float32x4_t __a)
+__arm_vrndmq_x_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return (float16x8_t) __a;
+ return __builtin_mve_vrndmq_m_fv4sf (vuninitializedq_f32 (), __a, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_s16 (int16x8_t __a)
+__arm_vrndpq_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return (float16x8_t) __a;
+ return __builtin_mve_vrndpq_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_s32 (int32x4_t __a)
+__arm_vrndpq_x_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return (float16x8_t) __a;
+ return __builtin_mve_vrndpq_m_fv4sf (vuninitializedq_f32 (), __a, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_s64 (int64x2_t __a)
+__arm_vrndaq_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return (float16x8_t) __a;
+ return __builtin_mve_vrndaq_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_s8 (int8x16_t __a)
+__arm_vrndaq_x_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return (float16x8_t) __a;
+ return __builtin_mve_vrndaq_m_fv4sf (vuninitializedq_f32 (), __a, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_u16 (uint16x8_t __a)
+__arm_vrndxq_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- return (float16x8_t) __a;
+ return __builtin_mve_vrndxq_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_u32 (uint32x4_t __a)
+__arm_vrndxq_x_f32 (float32x4_t __a, mve_pred16_t __p)
{
- return (float16x8_t) __a;
+ return __builtin_mve_vrndxq_m_fv4sf (vuninitializedq_f32 (), __a, __p);
}
__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_u64 (uint64x2_t __a)
+__arm_vandq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return (float16x8_t) __a;
+ return __builtin_mve_vandq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
-__extension__ extern __inline float16x8_t
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_u8 (uint8x16_t __a)
+__arm_vandq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return (float16x8_t) __a;
+ return __builtin_mve_vandq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_f16 (float16x8_t __a)
+__arm_vbicq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return (float32x4_t) __a;
+ return __builtin_mve_vbicq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_s16 (int16x8_t __a)
+__arm_vbicq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return (float32x4_t) __a;
+ return __builtin_mve_vbicq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_s32 (int32x4_t __a)
+__arm_vbrsrq_x_n_f16 (float16x8_t __a, int32_t __b, mve_pred16_t __p)
{
- return (float32x4_t) __a;
+ return __builtin_mve_vbrsrq_m_n_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_s64 (int64x2_t __a)
+__arm_vbrsrq_x_n_f32 (float32x4_t __a, int32_t __b, mve_pred16_t __p)
{
- return (float32x4_t) __a;
+ return __builtin_mve_vbrsrq_m_n_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_s8 (int8x16_t __a)
+__arm_veorq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return (float32x4_t) __a;
+ return __builtin_mve_veorq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_u16 (uint16x8_t __a)
+__arm_veorq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return (float32x4_t) __a;
+ return __builtin_mve_veorq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_u32 (uint32x4_t __a)
+__arm_vornq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return (float32x4_t) __a;
+ return __builtin_mve_vornq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_u64 (uint64x2_t __a)
+__arm_vornq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- return (float32x4_t) __a;
+ return __builtin_mve_vornq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_u8 (uint8x16_t __a)
+__arm_vorrq_x_f16 (float16x8_t __a, float16x8_t __b, mve_pred16_t __p)
{
- return (float32x4_t) __a;
+ return __builtin_mve_vorrq_m_fv8hf (vuninitializedq_f16 (), __a, __b, __p);
}
__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_gather_base_wb_f32 (uint32x4_t * __addr, const int __offset)
+__arm_vorrq_x_f32 (float32x4_t __a, float32x4_t __b, mve_pred16_t __p)
{
- float32x4_t
- result = __builtin_mve_vldrwq_gather_base_wb_fv4sf (*__addr, __offset);
- __addr += __offset;
- return result;
+ return __builtin_mve_vorrq_m_fv4sf (vuninitializedq_f32 (), __a, __b, __p);
}
-__extension__ extern __inline float32x4_t
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vldrwq_gather_base_wb_z_f32 (uint32x4_t * __addr, const int __offset, mve_pred16_t __p)
+__arm_vrev32q_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- float32x4_t
- result = __builtin_mve_vldrwq_gather_base_wb_z_fv4sf (*__addr, __offset, __p);
- __addr += __offset;
- return result;
+ return __builtin_mve_vrev32q_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline float16x8_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_scatter_base_wb_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value)
+__arm_vrev64q_x_f16 (float16x8_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_scatter_base_wb_fv4sf (*__addr, __offset, __value);
- __builtin_mve_vstrwq_scatter_base_wb_add_fv4sf (*__addr, __offset, *__addr);
+ return __builtin_mve_vrev64q_m_fv8hf (vuninitializedq_f16 (), __a, __p);
}
-__extension__ extern __inline void
+__extension__ extern __inline float32x4_t
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vstrwq_scatter_base_wb_p_f32 (uint32x4_t * __addr, const int __offset, float32x4_t __value, mve_pred16_t __p)
+__arm_vrev64q_x_f32 (float32x4_t __a, mve_pred16_t __p)
{
- __builtin_mve_vstrwq_scatter_base_wb_p_fv4sf (*__addr, __offset, __value, __p);
- __builtin_mve_vstrwq_scatter_base_wb_p_add_fv4sf (*__addr, __offset, *__addr, __p);
+ return __builtin_mve_vrev64q_m_fv4sf (vuninitializedq_f32 (), __a, __p);
}
#endif
@@ -18069,30 +21113,16 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vdupq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16_t), p2), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vdupq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32_t), p2));})
-#define vfmaq_n(p0,p1,p2) __arm_vfmaq_n(p0,p1,p2)
-#define __arm_vfmaq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
- __typeof(p1) __p1 = (p1); \
- __typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)));})
-
#define vfmaq(p0,p1,p2) __arm_vfmaq(p0,p1,p2)
#define __arm_vfmaq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
__typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)), \
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));})
-#define vfmasq_n(p0,p1,p2) __arm_vfmasq_n(p0,p1,p2)
-#define __arm_vfmasq_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
- __typeof(p1) __p1 = (p1); \
- __typeof(p2) __p2 = (p2); \
- _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
- int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \
- int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)));})
-
#define vfmsq(p0,p1,p2) __arm_vfmsq(p0,p1,p2)
#define __arm_vfmsq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -18101,6 +21131,14 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmsq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \
int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmsq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));})
+#define vfmasq(p0,p1,p2) __arm_vfmasq(p0,p1,p2)
+#define __arm_vfmasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t)), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t)));})
+
#define vmaxnmaq_m(p0,p1,p2) __arm_vmaxnmaq_m(p0,p1,p2)
#define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
__typeof(p1) __p1 = (p1); \
@@ -19154,6 +22192,306 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t]: __arm_vstrwq_scatter_base_wb_p_u32 (p0, p1, __ARM_mve_coerce(__p2, uint32x4_t), p3), \
int (*)[__ARM_mve_type_float32x4_t]: __arm_vstrwq_scatter_base_wb_p_f32 (p0, p1, __ARM_mve_coerce(__p2, float32x4_t), p3));})
+#define vabdq_x(p1,p2,p3) __arm_vabdq_x(p1,p2,p3)
+#define __arm_vabdq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vabdq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vabdq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vabsq_x(p1,p2) __arm_vabsq_x(p1,p2)
+#define __arm_vabsq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));})
+
+#define vaddq_x(p1,p2,p3) __arm_vaddq_x(p1,p2,p3)
+#define __arm_vaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));})
+
+#define vandq_x(p1,p2,p3) __arm_vandq_x(p1,p2,p3)
+#define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vandq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vandq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vbicq_x(p1,p2,p3) __arm_vbicq_x(p1,p2,p3)
+#define __arm_vbicq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vbicq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vbicq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vbrsrq_x(p1,p2,p3) __arm_vbrsrq_x(p1,p2,p3)
+#define __arm_vbrsrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vbrsrq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vbrsrq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vbrsrq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vbrsrq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2, p3));})
+
+#define vcaddq_rot270_x(p1,p2,p3) __arm_vcaddq_rot270_x(p1,p2,p3)
+#define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot270_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot270_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vcaddq_rot90_x(p1,p2,p3) __arm_vcaddq_rot90_x(p1,p2,p3)
+#define __arm_vcaddq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcaddq_rot90_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcaddq_rot90_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vcmulq_rot180_x(p1,p2,p3) __arm_vcmulq_rot180_x(p1,p2,p3)
+#define __arm_vcmulq_rot180_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot180_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot180_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vcmulq_rot270_x(p1,p2,p3) __arm_vcmulq_rot270_x(p1,p2,p3)
+#define __arm_vcmulq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot270_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot270_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vcmulq_x(p1,p2,p3) __arm_vcmulq_x(p1,p2,p3)
+#define __arm_vcmulq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vcvtq_x(p1,p2) __arm_vcvtq_x(p1,p2)
+#define __arm_vcvtq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_x_f16_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_x_f32_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_x_f16_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_x_f32_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));})
+
+#define vcvtq_x_n(p1,p2,p3) __arm_vcvtq_x_n(p1,p2,p3)
+#define __arm_vcvtq_x_n(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vcvtq_x_n_f16_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vcvtq_x_n_f32_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vcvtq_x_n_f16_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vcvtq_x_n_f32_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
+#define veorq_x(p1,p2,p3) __arm_veorq_x(p1,p2,p3)
+#define __arm_veorq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_x_s8(__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_x_s16(__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_x_s32(__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_veorq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_veorq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vmaxnmq_x(p1,p2,p3) __arm_vmaxnmq_x(p1,p2,p3)
+#define __arm_vmaxnmq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmaxnmq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmaxnmq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vminnmq_x(p1,p2,p3) __arm_vminnmq_x(p1,p2,p3)
+#define __arm_vminnmq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vminnmq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vminnmq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vmulq_x(p1,p2,p3) __arm_vmulq_x(p1,p2,p3)
+#define __arm_vmulq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));})
+
+#define vnegq_x(p1,p2) __arm_vnegq_x(p1,p2)
+#define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));})
+
+#define vornq_x(p1,p2,p3) __arm_vornq_x(p1,p2,p3)
+#define __arm_vornq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vornq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vornq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vorrq_x(p1,p2,p3) __arm_vorrq_x(p1,p2,p3)
+#define __arm_vorrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vorrq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vorrq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
+#define vrev32q_x(p1,p2) __arm_vrev32q_x(p1,p2)
+#define __arm_vrev32q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2));})
+
+#define vrev64q_x(p1,p2) __arm_vrev64q_x(p1,p2)
+#define __arm_vrev64q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2), \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));})
+
+#define vrndaq_x(p1,p2) __arm_vrndaq_x(p1,p2)
+#define __arm_vrndaq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndaq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndaq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));})
+
+#define vrndmq_x(p1,p2) __arm_vrndmq_x(p1,p2)
+#define __arm_vrndmq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndmq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndmq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));})
+
+#define vrndnq_x(p1,p2) __arm_vrndnq_x(p1,p2)
+#define __arm_vrndnq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndnq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndnq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));})
+
+#define vrndpq_x(p1,p2) __arm_vrndpq_x(p1,p2)
+#define __arm_vrndpq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndpq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndpq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));})
+
+#define vrndq_x(p1,p2) __arm_vrndq_x(p1,p2)
+#define __arm_vrndq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));})
+
+#define vrndxq_x(p1,p2) __arm_vrndxq_x(p1,p2)
+#define __arm_vrndxq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrndxq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), p2), \
+ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrndxq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), p2));})
+
+#define vsubq_x(p1,p2,p3) __arm_vsubq_x(p1,p2,p3)
+#define __arm_vsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16_t]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32_t]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32_t), p3));})
+
+#define vcmulq_rot90_x(p1,p2,p3) __arm_vcmulq_rot90_x(p1,p2,p3)
+#define __arm_vcmulq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmulq_rot90_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \
+ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmulq_rot90_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3));})
+
#else /* MVE Integer. */
#define vstrwq_scatter_base_wb(p0,p1,p2) __arm_vstrwq_scatter_base_wb(p0,p1,p2)
@@ -21648,8 +24986,509 @@ extern void *__ARM_undef;
int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));})
+#define vabsq_x(p1,p2) __arm_vabsq_x(p1,p2)
+#define __arm_vabsq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2));})
+
+#define vaddq_x(p1,p2,p3) __arm_vaddq_x(p1,p2,p3)
+#define __arm_vaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+
+#define vcaddq_rot270_x(p1,p2,p3) __arm_vcaddq_rot270_x(p1,p2,p3)
+#define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot270_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot270_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot270_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot270_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot270_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot270_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vcaddq_rot90_x(p1,p2,p3) __arm_vcaddq_rot90_x(p1,p2,p3)
+#define __arm_vcaddq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcaddq_rot90_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcaddq_rot90_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcaddq_rot90_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcaddq_rot90_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcaddq_rot90_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcaddq_rot90_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define veorq_x(p1,p2,p3) __arm_veorq_x(p1,p2,p3)
+#define __arm_veorq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_veorq_x_s8(__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_veorq_x_s16(__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_veorq_x_s32(__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_veorq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_veorq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_veorq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmaxq_x(p1,p2,p3) __arm_vmaxq_x(p1,p2,p3)
+#define __arm_vmaxq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmaxq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmaxq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmaxq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmaxq_x_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmaxq_x_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmaxq_x_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vminq_x(p1,p2,p3) __arm_vminq_x(p1,p2,p3)
+#define __arm_vminq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vminq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vminq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vminq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vminq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vminq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vminq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmovlbq_x(p1,p2) __arm_vmovlbq_x(p1,p2)
+#define __arm_vmovlbq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2));})
+
+#define vmovltq_x(p1,p2) __arm_vmovltq_x(p1,p2)
+#define __arm_vmovltq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2));})
+
+#define vmulhq_x(p1,p2,p3) __arm_vmulhq_x(p1,p2,p3)
+#define __arm_vmulhq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulhq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulhq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulhq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulhq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulhq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulhq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmullbq_int_x(p1,p2,p3) __arm_vmullbq_int_x(p1,p2,p3)
+#define __arm_vmullbq_int_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmullbq_int_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmullbq_int_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmullbq_int_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_int_x_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_int_x_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmullbq_int_x_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmullbq_poly_x(p1,p2,p3) __arm_vmullbq_poly_x(p1,p2,p3)
+#define __arm_vmullbq_poly_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmullbq_poly_x_p8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmullbq_poly_x_p16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));})
+
+#define vmulltq_int_x(p1,p2,p3) __arm_vmulltq_int_x(p1,p2,p3)
+#define __arm_vmulltq_int_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulltq_int_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulltq_int_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulltq_int_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_int_x_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_int_x_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulltq_int_x_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vmulltq_poly_x(p1,p2,p3) __arm_vmulltq_poly_x(p1,p2,p3)
+#define __arm_vmulltq_poly_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulltq_poly_x_p8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulltq_poly_x_p16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3));})
+
+#define vmulq_x(p1,p2,p3) __arm_vmulq_x(p1,p2,p3)
+#define __arm_vmulq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));})
+
+#define vnegq_x(p1,p2) __arm_vnegq_x(p1,p2)
+#define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2));})
+
+#define vornq_x(p1,p2,p3) __arm_vornq_x(p1,p2,p3)
+#define __arm_vornq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vornq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vornq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vornq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vornq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vornq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vornq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vorrq_x(p1,p2,p3) __arm_vorrq_x(p1,p2,p3)
+#define __arm_vorrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vorrq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vorrq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vorrq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vorrq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vorrq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vorrq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vrev32q_x(p1,p2) __arm_vrev32q_x(p1,p2)
+#define __arm_vrev32q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2));})
+
+#define vrev64q_x(p1,p2) __arm_vrev64q_x(p1,p2)
+#define __arm_vrev64q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));})
+
+#define vabdq_x(p1,p2,p3) __arm_vabdq_x(p1,p2,p3)
+#define __arm_vabdq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vabdq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vabdq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vabdq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vabdq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vabdq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vabdq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vandq_x(p1,p2,p3) __arm_vandq_x(p1,p2,p3)
+#define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vandq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vandq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vandq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vandq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vandq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vandq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vbicq_x(p1,p2,p3) __arm_vbicq_x(p1,p2,p3)
+#define __arm_vbicq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vbicq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vbicq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vbicq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vbicq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vbicq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vbicq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vbrsrq_x(p1,p2,p3) __arm_vbrsrq_x(p1,p2,p3)
+#define __arm_vbrsrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vbrsrq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vbrsrq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vbrsrq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vbrsrq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vbrsrq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vbrsrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
#endif /* MVE Integer. */
+#define vmvnq_x(p1,p2) __arm_vmvnq_x(p1,p2)
+#define __arm_vmvnq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));})
+
+#define vrev16q_x(p1,p2) __arm_vrev16q_x(p1,p2)
+#define __arm_vrev16q_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2));})
+
+#define vrhaddq_x(p1,p2,p3) __arm_vrhaddq_x(p1,p2,p3)
+#define __arm_vrhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrhaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrhaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrhaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vshlq_x(p0,p1,p2,p3) __arm_vshlq_x(p0,p1,p2,p3)
+#define __arm_vshlq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vshlq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vshlq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vshlq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vrmulhq_x(p1,p2,p3) __arm_vrmulhq_x(p1,p2,p3)
+#define __arm_vrmulhq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrmulhq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrmulhq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrmulhq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vrmulhq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vrmulhq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vrmulhq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vrshlq_x(p1,p2,p3) __arm_vrshlq_x(p1,p2,p3)
+#define __arm_vrshlq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vrshrq_x(p1,p2,p3) __arm_vrshrq_x(p1,p2,p3)
+#define __arm_vrshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vrshrq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vrshrq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vrshrq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrshrq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrshrq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrshrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
+#define vshllbq_x(p1,p2,p3) __arm_vshllbq_x(p1,p2,p3)
+#define __arm_vshllbq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vshllbq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vshllbq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshllbq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshllbq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3));})
+
+#define vshlltq_x(p1,p2,p3) __arm_vshlltq_x(p1,p2,p3)
+#define __arm_vshlltq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlltq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlltq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlltq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlltq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3));})
+
+#define vshlq_x_n(p1,p2,p3) __arm_vshlq_x_n(p1,p2,p3)
+#define __arm_vshlq_x_n(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vshlq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vshlq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vshlq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshlq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshlq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshlq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
+#define vdwdupq_x_u8(p1,p2,p3,p4) __arm_vdwdupq_x_u8(p1,p2,p3,p4)
+#define __arm_vdwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_x_n_u8 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+
+#define vdwdupq_x_u16(p1,p2,p3,p4) __arm_vdwdupq_x_u16(p1,p2,p3,p4)
+#define __arm_vdwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_x_n_u16 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+
+#define vdwdupq_x_u32(p1,p2,p3,p4) __arm_vdwdupq_x_u32(p1,p2,p3,p4)
+#define __arm_vdwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_vdwdupq_x_n_u32 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vdwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+
+#define viwdupq_x_u8(p1,p2,p3,p4) __arm_viwdupq_x_u8(p1,p2,p3,p4)
+#define __arm_viwdupq_x_u8(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_viwdupq_x_n_u8 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+
+#define viwdupq_x_u16(p1,p2,p3,p4) __arm_viwdupq_x_u16(p1,p2,p3,p4)
+#define __arm_viwdupq_x_u16(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_viwdupq_x_n_u16 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+
+#define viwdupq_x_u32(p1,p2,p3,p4) __arm_viwdupq_x_u32(p1,p2,p3,p4)
+#define __arm_viwdupq_x_u32(p1,p2,p3,p4) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_viwdupq_x_n_u32 (__ARM_mve_coerce(__p1, uint32_t), p2, p3, p4), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_viwdupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3, p4));})
+
+#define vidupq_x_u8(p1,p2,p3) __arm_vidupq_x_u8(p1,p2,p3)
+#define __arm_vidupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_vidupq_x_n_u8 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+
+#define vddupq_x_u8(p1,p2,p3) __arm_vddupq_x_u8(p1,p2,p3)
+#define __arm_vddupq_x_u8(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_vddupq_x_n_u8 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u8 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+
+#define vidupq_x_u16(p1,p2,p3) __arm_vidupq_x_u16(p1,p2,p3)
+#define __arm_vidupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_vidupq_x_n_u16 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+
+#define vddupq_x_u16(p1,p2,p3) __arm_vddupq_x_u16(p1,p2,p3)
+#define __arm_vddupq_x_u16(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_vddupq_x_n_u16 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u16 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+
+#define vidupq_x_u32(p1,p2,p3) __arm_vidupq_x_u32(p1,p2,p3)
+#define __arm_vidupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_vidupq_x_n_u32 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vidupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+
+#define vddupq_x_u32(p1,p2,p3) __arm_vddupq_x_u32(p1,p2,p3)
+#define __arm_vddupq_x_u32(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_uint32_t]: __arm_vddupq_x_n_u32 (__ARM_mve_coerce(__p1, uint32_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32_t_ptr]: __arm_vddupq_x_wb_u32 (__ARM_mve_coerce(__p1, uint32_t *), p2, p3));})
+
+#define vhaddq_x(p1,p2,p3) __arm_vhaddq_x(p1,p2,p3)
+#define vshrq_x(p1,p2,p3) __arm_vshrq_x(p1,p2,p3)
+#define __arm_vshrq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vshrq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vshrq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vshrq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vshrq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vshrq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2, p3), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vshrq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2, p3));})
+
+#define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhaddq_x_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vhcaddq_rot270_x(p1,p2,p3) __arm_vhcaddq_rot270_x(p1,p2,p3)
+#define __arm_vhcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot270_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot270_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot270_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vhcaddq_rot90_x(p1,p2,p3) __arm_vhcaddq_rot90_x(p1,p2,p3)
+#define __arm_vhcaddq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhcaddq_rot90_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhcaddq_rot90_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhcaddq_rot90_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));})
+
+#define vhsubq_x(p1,p2,p3) __arm_vhsubq_x(p1,p2,p3)
+#define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \
+ __typeof(p2) __p2 = (p2); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8_t]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16_t]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32_t]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8_t]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16_t]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32_t]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \
+ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \
+ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \
+ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \
+ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));})
+
+#define vclsq_x(p1,p2) __arm_vclsq_x(p1,p2)
+#define __arm_vclsq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2));})
+
+#define vclzq_x(p1,p2) __arm_vclzq_x(p1,p2)
+#define __arm_vclzq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
+ int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), p2), \
+ int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), p2), \
+ int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), p2));})
+
+#define vadciq(p0,p1,p2) __arm_vadciq(p0,p1,p2)
+#define __arm_vadciq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \
+ __typeof(p1) __p1 = (p1); \
+ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \
+ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vadciq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \
+ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vadciq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2));})
+
#define vstrdq_scatter_base_wb_p(p0,p1,p2,p3) __arm_vstrdq_scatter_base_wb_p(p0,p1,p2,p3)
#define __arm_vstrdq_scatter_base_wb_p(p0,p1,p2,p3) ({ __typeof(p2) __p2 = (p2); \
_Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 11b7afb55c3..adf53b3e245 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,381 @@
+2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
+
+ * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: New test.
+ * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vaddq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vandq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbicq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vclsq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vclsq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vclsq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vclzq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vclzq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vclzq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vclzq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vclzq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vclzq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/veorq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmulq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vnegq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vnegq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vnegq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vnegq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vnegq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vornq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vorrq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshlq_x_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_s16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_s8.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_u16.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsubq_x_u8.c: Likewise.
+
2020-03-20 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Andre Vieira <andre.simoesdiasvieira@arm.com>
Mihail Ionescu <mihail.ionescu@arm.com>
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
new file mode 100644
index 00000000000..2663db23994
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vabdq_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vabdq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
new file mode 100644
index 00000000000..0a5eb5c8d72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vabdq_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vabdq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
new file mode 100644
index 00000000000..3dd5e5d2717
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vabdq_x_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vabdq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
new file mode 100644
index 00000000000..9b1f30f1ae5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vabdq_x_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vabdq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
new file mode 100644
index 00000000000..0e386b5b46f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vabdq_x_s8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vabdq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
new file mode 100644
index 00000000000..ff7599a118a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vabdq_x_u16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.u16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vabdq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
new file mode 100644
index 00000000000..d93c0804652
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vabdq_x_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.u32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vabdq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
new file mode 100644
index 00000000000..73f89e4bd6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vabdq_x_u8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabdt.u8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vabdq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
new file mode 100644
index 00000000000..4fb74a827ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vabsq_x_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabst.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, mve_pred16_t p)
+{
+ return vabsq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
new file mode 100644
index 00000000000..2bad3c1515c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, mve_pred16_t p)
+{
+ return vabsq_x_f32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabst.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, mve_pred16_t p)
+{
+ return vabsq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
new file mode 100644
index 00000000000..84c0a8a3898
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, mve_pred16_t p)
+{
+ return vabsq_x_s16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabst.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vabsq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
new file mode 100644
index 00000000000..cf427a4e48b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, mve_pred16_t p)
+{
+ return vabsq_x_s32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabst.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+ return vabsq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
new file mode 100644
index 00000000000..a3fa9743495
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, mve_pred16_t p)
+{
+ return vabsq_x_s8 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vabst.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vabsq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
new file mode 100644
index 00000000000..ec3a85d9916
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vaddq_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
new file mode 100644
index 00000000000..b9b216cb9ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vaddq_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
new file mode 100644
index 00000000000..2e65cbf95ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+ return vaddq_x_n_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
new file mode 100644
index 00000000000..11243a62bd6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+ return vaddq_x_n_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
new file mode 100644
index 00000000000..0ef9afd490c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vaddq_x_n_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
new file mode 100644
index 00000000000..20b88a40d51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vaddq_x_n_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
new file mode 100644
index 00000000000..2bc90725c95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vaddq_x_n_s8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
new file mode 100644
index 00000000000..9e3ffb4c79e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vaddq_x_n_u16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
new file mode 100644
index 00000000000..ab5140e44ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vaddq_x_n_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
new file mode 100644
index 00000000000..0bdc00d0b4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vaddq_x_n_u8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
new file mode 100644
index 00000000000..c33c5cf0df1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vaddq_x_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
new file mode 100644
index 00000000000..458119051d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vaddq_x_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
new file mode 100644
index 00000000000..1aa65c9311c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vaddq_x_s8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
new file mode 100644
index 00000000000..eef9acc88a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vaddq_x_u16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
new file mode 100644
index 00000000000..e8e430bc6ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vaddq_x_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
new file mode 100644
index 00000000000..1b77145203c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vaddq_x_u8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vaddq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vaddt.i8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
new file mode 100644
index 00000000000..357e4b3c871
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vandq_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vandq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
new file mode 100644
index 00000000000..0e6cdf675a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vandq_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vandq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
new file mode 100644
index 00000000000..c18a19e8cf0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vandq_x_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vandq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
new file mode 100644
index 00000000000..3509dc78c3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vandq_x_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vandq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
new file mode 100644
index 00000000000..a4f0eece22b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vandq_x_s8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vandq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
new file mode 100644
index 00000000000..e85c5bd4ce8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vandq_x_u16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vandq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
new file mode 100644
index 00000000000..89430be4fca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vandq_x_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vandq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
new file mode 100644
index 00000000000..ab074c2b195
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vandq_x_u8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vandt" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vandq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
new file mode 100644
index 00000000000..12036af29df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vbicq_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vbicq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
new file mode 100644
index 00000000000..784653fa20d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vbicq_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vbicq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
new file mode 100644
index 00000000000..b0b34aea5d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vbicq_x_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vbicq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
new file mode 100644
index 00000000000..c023cfaca80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vbicq_x_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vbicq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
new file mode 100644
index 00000000000..3355dc625c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vbicq_x_s8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vbicq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
new file mode 100644
index 00000000000..abdcf002141
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vbicq_x_u16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vbicq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
new file mode 100644
index 00000000000..2aa34c50809
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vbicq_x_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vbicq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
new file mode 100644
index 00000000000..26c9e2ced9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vbicq_x_u8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbict" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vbicq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
new file mode 100644
index 00000000000..282837a1495
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x_n_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
new file mode 100644
index 00000000000..74ef4e61cea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x_n_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
new file mode 100644
index 00000000000..7f9dc4e773b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x_n_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
new file mode 100644
index 00000000000..4a4ffded8e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x_n_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
new file mode 100644
index 00000000000..db1f6ab8994
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x_n_s8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
new file mode 100644
index 00000000000..1bce070883c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x_n_u16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
new file mode 100644
index 00000000000..6e059c75d7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x_n_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
new file mode 100644
index 00000000000..aed3136d051
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x_n_u8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, int32_t b, mve_pred16_t p)
+{
+ return vbrsrq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vbrsrt.8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c
new file mode 100644
index 00000000000..60a96ada068
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c
new file mode 100644
index 00000000000..b79e7d03ef3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c
new file mode 100644
index 00000000000..efc58205c59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c
new file mode 100644
index 00000000000..25cf2ef5f6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c
new file mode 100644
index 00000000000..8dbdf137f61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x_s8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c
new file mode 100644
index 00000000000..13d9aa03204
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x_u16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c
new file mode 100644
index 00000000000..887133e575b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c
new file mode 100644
index 00000000000..e23cbab797c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x_u8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c
new file mode 100644
index 00000000000..2c96c2ac77f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c
new file mode 100644
index 00000000000..6ed2793185d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c
new file mode 100644
index 00000000000..9983baed23c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x_s16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c
new file mode 100644
index 00000000000..658763c4de2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x_s32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c
new file mode 100644
index 00000000000..a63dbe621c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x_s8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c
new file mode 100644
index 00000000000..e256cba3831
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x_u16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c
new file mode 100644
index 00000000000..9361a980f8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x_u32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c
new file mode 100644
index 00000000000..0664c6e77a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x_u8 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcaddt.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p)
+{
+ return vcaddq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c
new file mode 100644
index 00000000000..e956fe2de4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, mve_pred16_t p)
+{
+ return vclsq_x_s16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vclst.s16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vclsq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c
new file mode 100644
index 00000000000..cc0037986f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, mve_pred16_t p)
+{
+ return vclsq_x_s32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vclst.s32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+ return vclsq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c
new file mode 100644
index 00000000000..262e04c6a15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, mve_pred16_t p)
+{
+ return vclsq_x_s8 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vclst.s8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vclsq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c
new file mode 100644
index 00000000000..782d385b2f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (int16x8_t a, mve_pred16_t p)
+{
+ return vclzq_x_s16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vclzt.i16" } } */
+
+int16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vclzq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c
new file mode 100644
index 00000000000..cb96176a6dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (int32x4_t a, mve_pred16_t p)
+{
+ return vclzq_x_s32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vclzt.i32" } } */
+
+int32x4_t
+foo1 (int32x4_t a, mve_pred16_t p)
+{
+ return vclzq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c
new file mode 100644
index 00000000000..ee7ab8f86fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int8x16_t
+foo (int8x16_t a, mve_pred16_t p)
+{
+ return vclzq_x_s8 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vclzt.i8" } } */
+
+int8x16_t
+foo1 (int8x16_t a, mve_pred16_t p)
+{
+ return vclzq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c
new file mode 100644
index 00000000000..d4074abe6e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (uint16x8_t a, mve_pred16_t p)
+{
+ return vclzq_x_u16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vclzt.i16" } } */
+
+uint16x8_t
+foo1 (uint16x8_t a, mve_pred16_t p)
+{
+ return vclzq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c
new file mode 100644
index 00000000000..97112691529
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (uint32x4_t a, mve_pred16_t p)
+{
+ return vclzq_x_u32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vclzt.i32" } } */
+
+uint32x4_t
+foo1 (uint32x4_t a, mve_pred16_t p)
+{
+ return vclzq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c
new file mode 100644
index 00000000000..baa8eddcecd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint8x16_t
+foo (uint8x16_t a, mve_pred16_t p)
+{
+ return vclzq_x_u8 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vclzt.i8" } } */
+
+uint8x16_t
+foo1 (uint8x16_t a, mve_pred16_t p)
+{
+ return vclzq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
new file mode 100644
index 00000000000..caed477d1ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcmulq_rot180_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcmulq_rot180_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
new file mode 100644
index 00000000000..21814ade0c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcmulq_rot180_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcmulq_rot180_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
new file mode 100644
index 00000000000..14f939109e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcmulq_rot270_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcmulq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
new file mode 100644
index 00000000000..af20dfcbcf6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcmulq_rot270_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcmulq_rot270_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
new file mode 100644
index 00000000000..a7fd38043f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcmulq_rot90_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcmulq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
new file mode 100644
index 00000000000..6730cd76c5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcmulq_rot90_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcmulq_rot90_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
new file mode 100644
index 00000000000..18d32172bdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcmulq_x_f16 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f16" } } */
+
+float16x8_t
+foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
+{
+ return vcmulq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
new file mode 100644
index 00000000000..7162f4991d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcmulq_x_f32 (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcmult.f32" } } */
+
+float32x4_t
+foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
+{
+ return vcmulq_x (a, b, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
new file mode 100644
index 00000000000..ed4a0ed1299
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vcvtaq_x_s16_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtat.s16.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
new file mode 100644
index 00000000000..be969caf1b9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (float32x4_t a, mve_pred16_t p)
+{
+ return vcvtaq_x_s32_f32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtat.s32.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
new file mode 100644
index 00000000000..93038e94502
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vcvtaq_x_u16_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtat.u16.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
new file mode 100644
index 00000000000..421f238adfd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (float32x4_t a, mve_pred16_t p)
+{
+ return vcvtaq_x_u32_f32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtat.u32.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
new file mode 100644
index 00000000000..98e15cb6e3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float32x4_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vcvtbq_x_f32_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtbt.f32.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
new file mode 100644
index 00000000000..b017c0ee107
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vcvtmq_x_s16_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtmt.s16.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
new file mode 100644
index 00000000000..8e5e73cb728
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (float32x4_t a, mve_pred16_t p)
+{
+ return vcvtmq_x_s32_f32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtmt.s32.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
new file mode 100644
index 00000000000..a747745c65f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vcvtmq_x_u16_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtmt.u16.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
new file mode 100644
index 00000000000..7863427d40c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (float32x4_t a, mve_pred16_t p)
+{
+ return vcvtmq_x_u32_f32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtmt.u32.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
new file mode 100644
index 00000000000..b2b7230ce61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vcvtnq_x_s16_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtnt.s16.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
new file mode 100644
index 00000000000..e9f2fadcc32
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (float32x4_t a, mve_pred16_t p)
+{
+ return vcvtnq_x_s32_f32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtnt.s32.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
new file mode 100644
index 00000000000..05566182b52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vcvtnq_x_u16_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtnt.u16.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
new file mode 100644
index 00000000000..967bfb8ccda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (float32x4_t a, mve_pred16_t p)
+{
+ return vcvtnq_x_u32_f32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtnt.u32.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
new file mode 100644
index 00000000000..7ffe464cf7c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int16x8_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vcvtpq_x_s16_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtpt.s16.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
new file mode 100644
index 00000000000..0fe3380deb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+int32x4_t
+foo (float32x4_t a, mve_pred16_t p)
+{
+ return vcvtpq_x_s32_f32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtpt.s32.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
new file mode 100644
index 00000000000..77fd34c3edf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (float16x8_t a, mve_pred16_t p)
+{
+ return vcvtpq_x_u16_f16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtpt.u16.f16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
new file mode 100644
index 00000000000..369c9419a6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint32x4_t
+foo (float32x4_t a, mve_pred16_t p)
+{
+ return vcvtpq_x_u32_f32 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtpt.u32.f32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
new file mode 100644
index 00000000000..3c97d6e454a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (int16x8_t a, mve_pred16_t p)
+{
+ return vcvtq_x_f16_s16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
+
+float16x8_t
+foo1 (int16x8_t a, mve_pred16_t p)
+{
+ return vcvtq_x (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.f16.s16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
new file mode 100644
index 00000000000..14ca8c7b982
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+float16x8_t
+foo (uint16x8_t a, mve_pred16_t p)
+{
+ return vcvtq_x_f16_u16 (a, p);
+}
+
+/* { dg-final { scan-assembler "vpst" } } */
+/* { dg-final { scan-assembler "vcvtt.f16.u16" } }[...]
[diff truncated at 524288 bytes]
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