[gcc(refs/users/wschmidt/heads/builtins2)] More builtins.
William Schmidt
wschmidt@gcc.gnu.org
Mon Mar 23 02:14:22 GMT 2020
https://gcc.gnu.org/g:07d2a2503642d7babab2261e1ae11101a2e6b695
commit 07d2a2503642d7babab2261e1ae11101a2e6b695
Author: Bill Schmidt <wschmidt@linux.ibm.com>
Date: Sun Mar 22 21:13:26 2020 -0500
More builtins.
2020-03-22 Bill Schmidt <wschmidt@linux.ibm.com>
* gcc/config/rs6000/rs6000-builtin-new.def: More builtins.
* gcc/config/rs6000/rs6000-builtin.def: More comments.
Diff:
---
gcc/config/rs6000/rs6000-builtin-new.def | 91 ++++++++++++++++++++++++++++++++
gcc/config/rs6000/rs6000-builtin.def | 7 +++
2 files changed, 98 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def
index 7c1053da9dc..70542c4826f 100644
--- a/gcc/config/rs6000/rs6000-builtin-new.def
+++ b/gcc/config/rs6000/rs6000-builtin-new.def
@@ -1226,6 +1226,32 @@
const vf __builtin_vsx_floato_v2di (vsll);
FLOATO_V2DI floatov2di {}
+; #### For the following, currently the pattern is selected differently
+; depending on big-endian (e.g., vsx_load_v1ti) versus little-endian
+; (e.g, vsx_ld_elemrev_v1ti). We need to move the choice into a separate
+; pattern for each of these instead. Right now I only list the little-
+; endian pattern here. TBD.
+ pure vsq __builtin_vsx_ld_elemrev_v1ti (signed long long, void *);
+ LD_ELEMREV_V1TI vsx_ld_elemrev_v1ti {ldvec}
+
+ pure vd __builtin_vsx_ld_elemrev_v2df (signed long long, void *);
+ LD_ELEMREV_V2DF vsx_ld_elemrev_v2df {ldvec}
+
+ pure vsll __builtin_vsx_ld_elemrev_v2di (signed long long, void *);
+ LD_ELEMREV_V2DI vsx_ld_elemrev_v2di {ldvec}
+
+ pure vf __builtin_vsx_ld_elemrev_v4sf (signed long long, void *);
+ LD_ELEMREV_V4SF vsx_ld_elemrev_v4sf {ldvec}
+
+ pure vsi __builtin_vsx_ld_elemrev_v4si (signed long long, void *);
+ LD_ELEMREV_V4SI vsx_ld_elemrev_v4si {ldvec}
+
+ pure vss __builtin_vsx_ld_elemrev_v8hi (signed long long, void *);
+ LD_ELEMREV_V8HI vsx_ld_elemrev_v8hi {ldvec}
+
+ pure vsc __builtin_vsx_ld_elemrev_v16qi (signed long long, void *);
+ LD_ELEMREV_V16QI vsx_ld_elemrev_v16qi {ldvec}
+
; There is apparent intent in rs6000-builtin.def to have RS6000_BTC_SPECIAL
; processing for LXSDX, LXVDSX, and STXSDX, but there are no def_builtin calls
; for any of them. At some point, we may want to add a set of built-ins for
@@ -1291,6 +1317,32 @@
const vull __builtin_vsx_splat_2di_uns (unsigned long long);
SPLAT_2DI_UNS vsx_splat_v2di {}
+; #### For the following, currently the pattern is selected differently
+; depending on big-endian (e.g., vsx_store_v1ti) versus little-endian
+; (e.g, vsx_st_elemrev_v1ti). We need to move the choice into a separate
+; pattern for each of these instead. Right now I only list the little-
+; endian pattern here. TBD.
+ void __builtin_vsx_st_elemrev_v1ti (vsq, signed long long, void *);
+ ST_ELEMREV_V1TI vsx_st_elemrev_v1ti {stvec}
+
+ void __builtin_vsx_st_elemrev_v2df (vd, signed long long, void *);
+ ST_ELEMREV_V2DF vsx_st_elemrev_v2df {stvec}
+
+ void __builtin_vsx_st_elemrev_v2di (vsll, signed long long, void *);
+ ST_ELEMREV_V2DI vsx_st_elemrev_v2di {stvec}
+
+ void __builtin_vsx_st_elemrev_v4sf (vf, signed long long, void *);
+ ST_ELEMREV_V4SF vsx_st_elemrev_v4sf {stvec}
+
+ void __builtin_vsx_st_elemrev_v4si (vsi, signed long long, void *);
+ ST_ELEMREV_V4SI vsx_st_elemrev_v4si {stvec}
+
+ void __builtin_vsx_st_elemrev_v8hi (vss, signed long long, void *);
+ ST_ELEMREV_V8HI vsx_st_elemrev_v8hi {stvec}
+
+ void __builtin_vsx_st_elemrev_v16qi (vsc, signed long long, void *);
+ ST_ELEMREV_V16QI vsx_st_elemrev_v16qi {stvec}
+
void __builtin_vsx_stxvd2x_v1ti (vsq, signed long long, void *);
STXVD2X_V1TI vsx_store_v1ti {stvec}
@@ -1300,6 +1352,18 @@
void __builtin_vsx_stxvd2x_v2di (vsll, signed long long, void *);
STXVD2X_V2DI vsx_store_v2di {stvec}
+ void __builtin_vsx_stxvw4x_v4sf (vf, signed long long, void *);
+ STXVW4X_V4SF vsx_store_v4sf {stvec}
+
+ void __builtin_vsx_stxvw4x_v4si (vsi, signed long long, void *);
+ STXVW4X_V4SI vsx_store_v4si {stvec}
+
+ void __builtin_vsx_stxvw4x_v8hi (vss, signed long long, void *);
+ STXVW4X_V8HI vsx_store_v8hi {stvec}
+
+ void __builtin_vsx_stxvw4x_v16qi (vsc, signed long long, void *);
+ STXVW4X_V16QI vsx_store_v16qi {stvec}
+
const vull __builtin_vsx_udiv_2di (vull, vull);
UDIV_V2DI vsx_udiv_v2di {}
@@ -1321,6 +1385,33 @@
const vf __builtin_vsx_uns_floato_v2di (vull);
UNS_FLOATO_V2DI unsfloatov2di {}
+ const signed __int128 __builtin_vsx_vec_ext_v1ti (vsq, signed int);
+ VEC_EXT_V1TI nothing {extract}
+
+ const double __builtin_vsx_vec_ext_v2df (vd, signed int);
+ VEC_EXT_V2DF nothing {extract}
+
+ const signed long long __builtin_vsx_vec_ext_v2di (vsll, signed int);
+ VEC_EXT_V2DI nothing {extract}
+
+ const vsq __builtin_vsx_vec_init_v1ti (signed __int128);
+ VEC_INIT_V1TI nothing {init}
+
+ const vd __builtin_vsx_vec_init_v2df (double, double);
+ VEC_INIT_V2DF nothing {init}
+
+ const vsll __builtin_vsx_vec_init_v2di (signed long long, signed long long);
+ VEC_INIT_V2DI nothing {init}
+
+ const vsq __builtin_vsx_vec_set_v1ti (vsq, signed __int128, const int<0,0>);
+ VEC_SET_V1TI nothing {set}
+
+ const vd __builtin_vsx_vec_set_v2df (vd, double, const int<1>);
+ VEC_SET_V2DF nothing {set}
+
+ const vsll __builtin_vsx_vec_set_v2di (vsll, signed long long, const int<1>);
+ VEC_SET_V2DI nothing {set}
+
const vsll __builtin_vsx_vsigned_v2df (vd);
VEC_VSIGNED_V2DF vsx_xvcvdpsxds {}
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 2d542e1d5d3..59bb0e6f813 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1801,6 +1801,12 @@ BU_VSX_X (ST_ELEMREV_V4SF, "st_elemrev_v4sf", MEM)
BU_VSX_X (ST_ELEMREV_V4SI, "st_elemrev_v4si", MEM)
BU_VSX_X (ST_ELEMREV_V8HI, "st_elemrev_v8hi", MEM)
BU_VSX_X (ST_ELEMREV_V16QI, "st_elemrev_v16qi", MEM)
+; #### Following builtins appear to be orphaned with no implementation.
+; They are all marked as requiring special handling, but there is no
+; special handling for them. For now I am not sure we really miss
+; anything by not having these; they all have regular float counterparts
+; and there is little utility in forcing these with builtins. No plan
+; to put them in rs6000-builtins-new.def.
BU_VSX_X (XSABSDP, "xsabsdp", CONST)
BU_VSX_X (XSADDDP, "xsadddp", FP)
BU_VSX_X (XSCMPODP, "xscmpodp", FP)
@@ -1825,6 +1831,7 @@ BU_VSX_X (XSNMADDMDP, "xsnmaddmdp", FP)
BU_VSX_X (XSNMSUBADP, "xsnmsubadp", FP)
BU_VSX_X (XSNMSUBMDP, "xsnmsubmdp", FP)
BU_VSX_X (XSSUBDP, "xssubdp", FP)
+; #### End orphaned builtins.
BU_VSX_X (VEC_INIT_V1TI, "vec_init_v1ti", CONST)
BU_VSX_X (VEC_INIT_V2DF, "vec_init_v2df", CONST)
BU_VSX_X (VEC_INIT_V2DI, "vec_init_v2di", CONST)
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