[gcc r10-7072] [AArch64] Fix lane specifier syntax
Wilco Dijkstra
wilco@gcc.gnu.org
Fri Mar 6 18:44:00 GMT 2020
https://gcc.gnu.org/g:3e5c062e96c11a6eaef1cbf94b5992391a850dbf
commit r10-7072-g3e5c062e96c11a6eaef1cbf94b5992391a850dbf
Author: Wilco Dijkstra <wdijkstr@arm.com>
Date: Fri Mar 6 18:19:46 2020 +0000
[AArch64] Fix lane specifier syntax
The syntax for lane specifiers uses a vector element rather than a vector:
fmls v0.2s, v1.2s, v1.s[1] // rather than v1.2s[1]
Fix all the lane specifiers to use Vetype which uses the correct element type.
gcc/
* aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
(aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
(aarch64_mls_elt<mode>): Likewise.
(aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fma4_elt<mode>): Likewise.
(aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fma4_elt_to_64v2df): Likewise.
(aarch64_fnma4_elt<mode>): Likewise.
(aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fnma4_elt_to_64v2df): Likewise.
testsuite/
* gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax.
* gcc.target/aarch64/fmls_intrinsic_1.c: Likewise.
* gcc.target/aarch64/mla_intrinsic_1.c: Likewise.
* gcc.target/aarch64/mls_intrinsic_1.c: Likewise.
Diff:
---
gcc/ChangeLog | 13 +++++++++++++
gcc/config/aarch64/aarch64-simd.md | 20 ++++++++++----------
gcc/testsuite/ChangeLog | 7 +++++++
gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c | 6 +++---
gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c | 6 +++---
gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c | 4 ++--
gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c | 4 ++--
7 files changed, 40 insertions(+), 20 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 957c4cc..1cb6694 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
+ (aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
+ (aarch64_mls_elt<mode>): Likewise.
+ (aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
+ (aarch64_fma4_elt<mode>): Likewise.
+ (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
+ (aarch64_fma4_elt_to_64v2df): Likewise.
+ (aarch64_fnma4_elt<mode>): Likewise.
+ (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
+ (aarch64_fnma4_elt_to_64v2df): Likewise.
+
2020-03-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-sve2.md (@aarch64_sve_<sve_int_op><mode>:
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 035f316..e5cf4e4 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1350,7 +1350,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -1368,7 +1368,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
- return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ return "mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -1408,7 +1408,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -1426,7 +1426,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
- return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ return "mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_mla_<Vetype>_scalar<q>")]
)
@@ -2003,7 +2003,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -2020,7 +2020,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
- return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ return "fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -2048,7 +2048,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
- return "fmla\\t%0.2d, %3.2d, %1.2d[%2]";
+ return "fmla\\t%0.2d, %3.2d, %1.d[%2]";
}
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
@@ -2077,7 +2077,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[2]));
- return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -2095,7 +2095,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (<VSWAP_WIDTH>mode, INTVAL (operands[2]));
- return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]";
+ return "fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vetype>[%2]";
}
[(set_attr "type" "neon_fp_mla_<Vetype>_scalar<q>")]
)
@@ -2125,7 +2125,7 @@
"TARGET_SIMD"
{
operands[2] = aarch64_endian_lane_rtx (V2DFmode, INTVAL (operands[2]));
- return "fmls\\t%0.2d, %3.2d, %1.2d[%2]";
+ return "fmls\\t%0.2d, %3.2d, %1.d[%2]";
}
[(set_attr "type" "neon_fp_mla_d_scalar_q")]
)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ea9bc42..59c9988 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-03-06 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax.
+ * gcc.target/aarch64/fmls_intrinsic_1.c: Likewise.
+ * gcc.target/aarch64/mla_intrinsic_1.c: Likewise.
+ * gcc.target/aarch64/mls_intrinsic_1.c: Likewise.
+
2020-03-06 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/tumaddsidi4.c: Step-up optimization level.
diff --git a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
index 5b34882..59ad41e 100644
--- a/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
@@ -98,11 +98,11 @@ main (int argc, char **argv)
/* vfma_laneq_f32.
vfma_lane_f32. */
-/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
/* vfmaq_lane_f32.
vfmaq_laneq_f32. */
-/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
/* vfma_lane_f64. */
/* { dg-final { scan-assembler-times "fmadd\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
@@ -110,6 +110,6 @@ main (int argc, char **argv)
/* vfmaq_lane_f64.
vfma_laneq_f64.
vfmaq_laneq_f64. */
-/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
+/* { dg-final { scan-assembler-times "fmla\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
index 6c194a0..2d5a3d3 100644
--- a/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
@@ -99,11 +99,11 @@ main (int argc, char **argv)
/* vfms_laneq_f32.
vfms_lane_f32. */
-/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.2s\\\[\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
/* vfmsq_lane_f32.
vfmsq_laneq_f32. */
-/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 2 } } */
/* vfms_lane_f64. */
/* { dg-final { scan-assembler-times "fmsub\\td\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+\, d\[0-9\]+" 1 } } */
@@ -111,6 +111,6 @@ main (int argc, char **argv)
/* vfmsq_lane_f64.
vfms_laneq_f64.
vfmsq_laneq_f64. */
-/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.2?d\\\[\[0-9\]+\\\]" 3 } } */
+/* { dg-final { scan-assembler-times "fmls\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d, v\[0-9\]+\.d\\\[\[0-9\]+\\\]" 3 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
index 4bdfac7..46b3c78 100644
--- a/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
@@ -78,6 +78,6 @@ main (int argc, char **argv)
return 0;
}
-/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
-/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mla\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c b/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
index 4b13faf..e01a4f6 100644
--- a/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c
@@ -83,6 +83,6 @@ main (int argc, char **argv)
return 0;
}
-/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s\\\[\[0-9\]+\\\]" 4 } } */
-/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.s\\\[\[0-9\]+\\\]" 4 } } */
+/* { dg-final { scan-assembler-times "mls\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.h\\\[\[0-9\]+\\\]" 4 } } */
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