[gcc/devel/omp/gcc-9] mips.md (mips_get_fcsr, [...]): Use SI machine mode for unspec_volatile operand.

[Tobias Burnus]

https://gcc.gnu.org/g:e5bd4faa8bbe50e66105e1a14d38f3e884de74ef

commit e5bd4faa8bbe50e66105e1a14d38f3e884de74ef
Author: Mihailo Stojanovic <mistojanovic@wavecomp.com>
Date:   Fri Aug 23 19:09:07 2019 +0000

    mips.md (mips_get_fcsr, [...]): Use SI machine mode for unspec_volatile operand.
    
            * config/mips/mips.md (mips_get_fcsr, *mips_get_fcsr): Use SI
            machine mode for unspec_volatile operand.
    
            * gcc.target/mips/get-fcsr-3.c: New test.
    
    From-SVN: r274864

Diff:
---
 gcc/ChangeLog                              | 8 ++++++++
 gcc/config/mips/mips.md                    | 4 ++--
 gcc/testsuite/ChangeLog                    | 4 ++++
 gcc/testsuite/gcc.target/mips/get-fcsr-3.c | 9 +++++++++
 4 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cfc39d6..44d8399 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-08-23  Mihailo Stojanovic  <mistojanovic@wavecomp.com>
+
+	Backport from mainline
+	2019-08-23  Mihailo Stojanovic  <mistojanovic@wavecomp.com>
+
+	* config/mips/mips.md (mips_get_fcsr, *mips_get_fcsr): Use SI
+	machine mode for unspec_volatile operand.
+
 2019-08-23  Martin Liska  <mliska@suse.cz>
 
 	PR ipa/91508
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 2ae1f7e..a9b0c86 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -7588,7 +7588,7 @@
 ;; __builtin_mips_get_fcsr: move the FCSR into operand 0.
 (define_expand "mips_get_fcsr"
   [(set (match_operand:SI 0 "register_operand")
-  	(unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
+       (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))]
   "TARGET_HARD_FLOAT_ABI"
 {
   if (TARGET_MIPS16)
@@ -7600,7 +7600,7 @@
 
 (define_insn "*mips_get_fcsr"
   [(set (match_operand:SI 0 "register_operand" "=d")
-  	(unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
+       (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))]
   "TARGET_HARD_FLOAT"
   "cfc1\t%0,$31")
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8073e23..bf696ab 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2019-08-23  Mihailo Stojanovic  <mistojanovic@wavecomp.com>
+
+	* gcc.target/mips/get-fcsr-3.c: New test.
+
 2019-08-20  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* gcc.c-torture/execute/20190820-1.c: New test.
diff --git a/gcc/testsuite/gcc.target/mips/get-fcsr-3.c b/gcc/testsuite/gcc.target/mips/get-fcsr-3.c
new file mode 100644
index 0000000..7bb97b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/get-fcsr-3.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mabi=64 -mhard-float" } */
+
+NOMIPS16 unsigned int
+foo (void)
+{
+  return __builtin_mips_get_fcsr () & 0x1;
+}
+
+/* { dg-final { scan-assembler "cfc1" } } */