[gcc(refs/users/segher/heads/cc0)] doc: Some CC0 fixes
Segher Boessenkool
segher@gcc.gnu.org
Mon Jun 15 19:24:22 GMT 2020
https://gcc.gnu.org/g:71e5e350d3991a19b540a22b5b2644175c4a9f4d
commit 71e5e350d3991a19b540a22b5b2644175c4a9f4d
Author: Segher Boessenkool <segher@kernel.crashing.org>
Date: Mon Sep 23 01:29:49 2019 +0000
doc: Some CC0 fixes
Diff:
---
gcc/doc/md.texi | 4 +-
gcc/doc/rtl.texi | 141 ++++++++---------------------------------------------
gcc/doc/tm.texi | 21 +++-----
gcc/doc/tm.texi.in | 19 +++-----
4 files changed, 36 insertions(+), 149 deletions(-)
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index fcc3c68048a..6eb52d0f340 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -6815,7 +6815,7 @@ such as
[(set (pc)
(if_then_else (match_operator
0 "comparison_operator"
- [(cc0) (const_int 0)])
+ [(reg:CC CC_REG) (const_int 0)])
(return)
(pc)))]
"@var{condition}"
@@ -7928,7 +7928,7 @@ the operations as far as possible. For instance,
@cindex @code{compare}, canonicalization of
@item
For the @code{compare} operator, a constant is always the second operand
-if the first argument is a condition code register or @code{(cc0)}.
+if the first argument is a condition code register.
@item
For instructions that inherently set a condition code register, the
diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 2570cd34281..64a5a743cb7 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc/rtl.texi
@@ -1270,8 +1270,7 @@ accumulator. The default format is ``64.64''.
``Condition Code'' mode represents the value of a condition code, which
is a machine-specific set of bits used to represent the result of a
comparison operation. Other machine-specific modes may also be used for
-the condition code. These modes are not used on machines that use
-@code{cc0} (@pxref{Condition Code}).
+the condition code. (@pxref{Condition Code}).
@findex BLKmode
@item BLKmode
@@ -2293,51 +2292,17 @@ the reload pass.
@code{scratch} is usually present inside a @code{clobber} operation
(@pxref{Side Effects}).
-@findex cc0
-@cindex condition code register
-@item (cc0)
-This refers to the machine's condition code register. It has no
-operands and may not have a machine mode. There are two ways to use it:
-
-@itemize @bullet
-@item
-To stand for a complete set of condition code flags. This is best on
-most machines, where each comparison sets the entire series of flags.
-
-With this technique, @code{(cc0)} may be validly used in only two
-contexts: as the destination of an assignment (in test and compare
-instructions) and in comparison operators comparing against zero
-(@code{const_int} with value zero; that is to say, @code{const0_rtx}).
-
-@item
-To stand for a single flag that is the result of a single condition.
-This is useful on machines that have only a single flag bit, and in
-which comparison instructions must specify the condition to test.
-
-With this technique, @code{(cc0)} may be validly used in only two
-contexts: as the destination of an assignment (in test and compare
-instructions) where the source is a comparison operator, and as the
-first operand of @code{if_then_else} (in a conditional branch).
-@end itemize
-
-@findex cc0_rtx
-There is only one expression object of code @code{cc0}; it is the
-value of the variable @code{cc0_rtx}. Any attempt to create an
-expression of code @code{cc0} will return @code{cc0_rtx}.
-
On some machines, the condition code register is given a register number
-and a @code{reg} is used instead of @code{(cc0)}. This is usually the
-preferable approach if only a small subset of instructions modify the
-condition code. Other machines store condition codes in general
+and a @code{reg} is used.
+Other machines store condition codes in general
registers; in such cases a pseudo register should be used.
Some machines, such as the SPARC and RS/6000, have two sets of
arithmetic instructions, one that sets and one that does not set the
condition code. This is best handled by normally generating the
instruction that does not set the condition code, and making a pattern
-that both performs the arithmetic and sets the condition code register
-(which would not be @code{(cc0)} in this case). For examples, search
-for @samp{addcc} and @samp{andcc} in @file{sparc.md}.
+that both performs the arithmetic and sets the condition code register.
+For examples, search for @samp{addcc} and @samp{andcc} in @file{sparc.md}.
@findex pc
@item (pc)
@@ -2455,14 +2420,13 @@ Of course, machines cannot really subtract with infinite precision.
However, they can pretend to do so when only the sign of the result will
be used, which is the case when the result is stored in the condition
code. And that is the @emph{only} way this kind of expression may
-validly be used: as a value to be stored in the condition codes, either
-@code{(cc0)} or a register. @xref{Comparisons}.
+validly be used: as a value to be stored in the condition codes, in a
+register. @xref{Comparisons}.
The mode @var{m} is not related to the modes of @var{x} and @var{y}, but
-instead is the mode of the condition code value. If @code{(cc0)} is
-used, it is @code{VOIDmode}. Otherwise it is some mode in class
+instead is the mode of the condition code value. It is some mode in class
@code{MODE_CC}, often @code{CCmode}. @xref{Condition Code}. If @var{m}
-is @code{VOIDmode} or @code{CCmode}, the operation returns sufficient
+is @code{CCmode}, the operation returns sufficient
information (in an unspecified format) so that any comparison operator
can be applied to the result of the @code{COMPARE} operation. For other
modes in class @code{MODE_CC}, the operation only returns a subset of
@@ -2757,26 +2721,17 @@ of the data being compared. If the comparison operation is being tested
@code{VOIDmode}.
@cindex condition codes
-There are two ways that comparison operations may be used. The
-comparison operators may be used to compare the condition codes
-@code{(cc0)} against zero, as in @code{(eq (cc0) (const_int 0))}. Such
-a construct actually refers to the result of the preceding instruction
-in which the condition codes were set. The instruction setting the
-condition code must be adjacent to the instruction using the condition
-code; only @code{note} insns may separate them.
-
-Alternatively, a comparison operation may directly compare two data
+A comparison operation compares two data
objects. The mode of the comparison is determined by the operands; they
must both be valid for a common machine mode. A comparison with both
operands constant would be invalid as the machine mode could not be
deduced from it, but such a comparison should never exist in RTL due to
constant folding.
-In the example above, if @code{(cc0)} were last set to
-@code{(compare @var{x} @var{y})}, the comparison operation is
-identical to @code{(eq @var{x} @var{y})}. Usually only one style
+Usually only one style
of comparisons is supported on a particular machine, but the combine
-pass will try to merge the operations to produce the @code{eq} shown
+pass will try to merge operations to produce code like
+@code{(eq @var{x} @var{y})},
in case it exists in the context of the particular insn involved.
Inequality comparisons come in two flavors, signed and unsigned. Thus,
@@ -3128,7 +3083,7 @@ Represents the action of storing the value of @var{x} into the place
represented by @var{lval}. @var{lval} must be an expression
representing a place that can be stored in: @code{reg} (or @code{subreg},
@code{strict_low_part} or @code{zero_extract}), @code{mem}, @code{pc},
-@code{parallel}, or @code{cc0}.
+or @code{parallel}.
If @var{lval} is a @code{reg}, @code{subreg} or @code{mem}, it has a
machine mode; then @var{x} must be valid for that mode.
@@ -3151,13 +3106,6 @@ the bit-field (a memory or register reference) specified by the
bit-field is not changed. Note that @code{sign_extract} cannot
appear in @var{lval}.
-If @var{lval} is @code{(cc0)}, it has no machine mode, and @var{x} may
-be either a @code{compare} expression or a value that may have any mode.
-The latter case represents a ``test'' instruction. The expression
-@code{(set (cc0) (reg:@var{m} @var{n}))} is equivalent to
-@code{(set (cc0) (compare (reg:@var{m} @var{n}) (const_int 0)))}.
-Use the former expression to save space during the compilation.
-
If @var{lval} is a @code{parallel}, it is used to represent the case of
a function returning a structure in multiple registers. Each element
of the @code{parallel} is an @code{expr_list} whose first operand is a
@@ -3179,7 +3127,7 @@ does not jump) and the other of the two must be a @code{label_ref}
@code{mem}; these unusual patterns are used to represent jumps through
branch tables.
-If @var{lval} is neither @code{(cc0)} nor @code{(pc)}, the mode of
+If @var{lval} is not @code{(pc)}, the mode of
@var{lval} must not be @code{VOIDmode} and the mode of @var{x} must be
valid for the mode of @var{lval}.
@@ -3362,9 +3310,9 @@ For example, people sometimes attempt to represent a jump-if-zero
instruction this way:
@smallexample
-(parallel [(set (cc0) (reg:SI 34))
+(parallel [(set (reg:CC CC_REG) (reg:SI 34))
(set (pc) (if_then_else
- (eq (cc0) (const_int 0))
+ (eq (reg:CC CC_REG) (const_int 0))
(label_ref @dots{})
(pc)))])
@end smallexample
@@ -4059,14 +4007,6 @@ In the debugging output, this field is printed as a number followed by
a symbolic representation that locates the pattern in the @file{md}
file as some small positive or negative offset from a named pattern.
-@findex LOG_LINKS
-@item LOG_LINKS (@var{i})
-A list (chain of @code{insn_list} expressions) giving information about
-dependencies between instructions within a basic block. Neither a jump
-nor a label may come between the related insns. These are only used by
-the schedulers and by combine. This is a deprecated data structure.
-Def-use and use-def chains are now preferred.
-
@findex REG_NOTES
@item REG_NOTES (@var{i})
A list (chain of @code{expr_list}, @code{insn_list} and @code{int_list}
@@ -4074,23 +4014,9 @@ expressions) giving miscellaneous information about the insn. It is often
information pertaining to the registers used in this insn.
@end table
-The @code{LOG_LINKS} field of an insn is a chain of @code{insn_list}
-expressions. Each of these has two operands: the first is an insn,
-and the second is another @code{insn_list} expression (the next one in
-the chain). The last @code{insn_list} in the chain has a null pointer
-as second operand. The significant thing about the chain is which
-insns appear in it (as first operands of @code{insn_list}
-expressions). Their order is not significant.
-
-This list is originally set up by the flow analysis pass; it is a null
-pointer until then. Flow only adds links for those data dependencies
-which can be used for instruction combination. For each insn, the flow
-analysis pass adds a link to insns which store into registers values
-that are used for the first time in this insn.
-
-The @code{REG_NOTES} field of an insn is a chain similar to the
-@code{LOG_LINKS} field but it includes @code{expr_list} and @code{int_list}
-expressions in addition to @code{insn_list} expressions. There are several
+The @code{REG_NOTES} field of an insn is a chain that includes
+@code{expr_list} and @code{int_list} expressions as well as @code{insn_list}
+expressions. There are several
kinds of register notes, which are distinguished by the machine mode, which
in a register note is really understood as being an @code{enum reg_note}.
The first operand @var{op} of the note is data whose meaning depends on
@@ -4105,8 +4031,7 @@ register note. Its counterpart, the macro @code{PUT_REG_NOTE_KIND
Register notes are of three classes: They may say something about an
input to an insn, they may say something about an output of an insn, or
-they may create a linkage between two insns. There are also a set
-of values that are only used in @code{LOG_LINKS}.
+they may create a linkage between two insns.
These register notes annotate inputs to an insn:
@@ -4247,26 +4172,6 @@ These notes describe linkages between insns. They occur in pairs: one
insn has one of a pair of notes that points to a second insn, which has
the inverse note pointing back to the first insn.
-@table @code
-@findex REG_CC_SETTER
-@findex REG_CC_USER
-@item REG_CC_SETTER
-@itemx REG_CC_USER
-On machines that use @code{cc0}, the insns which set and use @code{cc0}
-set and use @code{cc0} are adjacent. However, when branch delay slot
-filling is done, this may no longer be true. In this case a
-@code{REG_CC_USER} note will be placed on the insn setting @code{cc0} to
-point to the insn using @code{cc0} and a @code{REG_CC_SETTER} note will
-be placed on the insn using @code{cc0} to point to the insn setting
-@code{cc0}.
-@end table
-
-These values are only used in the @code{LOG_LINKS} field, and indicate
-the type of dependency that each link represents. Links which indicate
-a data dependence (a read after write dependence) do not use any code,
-they simply have mode @code{VOIDmode}, and are printed without any
-descriptive text.
-
@table @code
@findex REG_DEP_TRUE
@item REG_DEP_TRUE
@@ -4444,10 +4349,6 @@ are shared.
@item
There is only one @code{pc} expression.
-@cindex @code{cc0}, RTL sharing
-@item
-There is only one @code{cc0} expression.
-
@cindex @code{const_double}, RTL sharing
@item
There is only one @code{const_double} expression with value 0 for
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 23aa9ad7963..88ab972e9e5 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -6280,21 +6280,16 @@ or target-specific sections.
@section Condition Code Status
@cindex condition code status
-The macros in this section can be split in two families, according to the
-two ways of representing condition codes in GCC.
-
-The first representation is the so called @code{(cc0)} representation
-(@pxref{Jump Patterns}), where all instructions can have an implicit
-clobber of the condition codes. The second is the condition code
-register representation, which provides better schedulability for
+Condition codes in GCC are represented as registers,
+which provides better schedulability for
architectures that do have a condition code register, but on which
most instructions do not affect it. The latter category includes
most RISC machines.
-The implicit clobbering poses a strong restriction on the placement of
+Implicit clobbering would pose a strong restriction on the placement of
the definition and use of the condition code. In the past the definition
and use were always adjacent. However, recent changes to support trapping
-arithmatic may result in the definition and user being in different blocks.
+arithmetic may result in the definition and user being in different blocks.
Thus, there may be a @code{NOTE_INSN_BASIC_BLOCK} between them. Additionally,
the definition may be the source of exception handling edges.
@@ -6305,8 +6300,7 @@ three instructions earlier than the conditional branch. The instruction
scheduler cannot perform this optimization if it is not permitted to
separate the definition and use of the condition code register.
-For this reason, it is possible and suggested to use a register to
-represent the condition code for new ports. If there is a specific
+If there is a specific
condition code register in the machine, use a hard register. If the
condition code or comparison result can be placed in any general register,
or if there are multiple condition registers, use a pseudo register.
@@ -6435,7 +6429,7 @@ like:
@end defmac
@deftypefn {Target Hook} bool TARGET_FIXED_CONDITION_CODE_REGS (unsigned int *@var{p1}, unsigned int *@var{p2})
-On targets which do not use @code{(cc0)}, and which use a hard
+On targets which use a hard
register rather than a pseudo-register to hold condition codes, the
regular CSE passes are often not able to identify cases in which the
hard register is set to a common value. Use this hook to enable a
@@ -11449,8 +11443,7 @@ for cross-profiling.
A C expression for the maximum number of instructions to execute via
conditional execution instructions instead of a branch. A value of
-@code{BRANCH_COST}+1 is the default if the machine does not use cc0, and
-1 if it does use cc0.
+@code{BRANCH_COST}+1 is the default.
@end defmac
@defmac IFCVT_MODIFY_TESTS (@var{ce_info}, @var{true_expr}, @var{false_expr})
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 5f684abfabc..28df8d38c4c 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -4262,21 +4262,16 @@ or @code{TARGET_MAX_ANCHOR_OFFSET} is set to a nonzero value.
@section Condition Code Status
@cindex condition code status
-The macros in this section can be split in two families, according to the
-two ways of representing condition codes in GCC.
-
-The first representation is the so called @code{(cc0)} representation
-(@pxref{Jump Patterns}), where all instructions can have an implicit
-clobber of the condition codes. The second is the condition code
-register representation, which provides better schedulability for
+Condition codes in GCC are represented as registers,
+which provides better schedulability for
architectures that do have a condition code register, but on which
most instructions do not affect it. The latter category includes
most RISC machines.
-The implicit clobbering poses a strong restriction on the placement of
+Implicit clobbering would pose a strong restriction on the placement of
the definition and use of the condition code. In the past the definition
and use were always adjacent. However, recent changes to support trapping
-arithmatic may result in the definition and user being in different blocks.
+arithmetic may result in the definition and user being in different blocks.
Thus, there may be a @code{NOTE_INSN_BASIC_BLOCK} between them. Additionally,
the definition may be the source of exception handling edges.
@@ -4287,8 +4282,7 @@ three instructions earlier than the conditional branch. The instruction
scheduler cannot perform this optimization if it is not permitted to
separate the definition and use of the condition code register.
-For this reason, it is possible and suggested to use a register to
-represent the condition code for new ports. If there is a specific
+If there is a specific
condition code register in the machine, use a hard register. If the
condition code or comparison result can be placed in any general register,
or if there are multiple condition registers, use a pseudo register.
@@ -7816,8 +7810,7 @@ for cross-profiling.
A C expression for the maximum number of instructions to execute via
conditional execution instructions instead of a branch. A value of
-@code{BRANCH_COST}+1 is the default if the machine does not use cc0, and
-1 if it does use cc0.
+@code{BRANCH_COST}+1 is the default.
@end defmac
@defmac IFCVT_MODIFY_TESTS (@var{ce_info}, @var{true_expr}, @var{false_expr})
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