[gcc(refs/vendors/ARM/heads/arm-perf-staging)] i386: Rename TARGET_USE_XCHG_FOR_ATOMIC_STORE to TARGET_AVOID_MFENCE.

[Tamar Christina]

https://gcc.gnu.org/g:4083981ebd9feb03c6ab8e7415429d4c4692da22

commit 4083981ebd9feb03c6ab8e7415429d4c4692da22
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Tue Jul 21 20:30:15 2020 +0200

    i386: Rename TARGET_USE_XCHG_FOR_ATOMIC_STORE to TARGET_AVOID_MFENCE.
    
    2020-07-21  Uroš Bizjak  <ubizjak@gmail.com>
    
    gcc/ChangeLog:
    
            * config/i386/i386.h (TARGET_AVOID_MFENCE):
            Rename from TARGET_USE_XCHG_FOR_ATOMIC_STORE.
            * config/i386/sync.md (atomic_store<mode>): Update for rename.
            * config/i386/x86-tune.def (X86_TUNE_AVOID_MFENCE):
            Rename from X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE.

Diff:
---
 gcc/config/i386/i386.h       | 3 +--
 gcc/config/i386/sync.md      | 5 ++---
 gcc/config/i386/x86-tune.def | 4 ++--
 3 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 23a513d8ffd..4ff8b5e6562 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -592,8 +592,7 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
 	ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI]
 #define TARGET_ONE_IF_CONV_INSN \
 	ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN]
-#define TARGET_USE_XCHG_FOR_ATOMIC_STORE \
-	ix86_tune_features[X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE]
+#define TARGET_AVOID_MFENCE ix86_tune_features[X86_TUNE_AVOID_MFENCE]
 #define TARGET_EMIT_VZEROUPPER \
 	ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER]
 #define TARGET_EXPAND_ABS \
diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 9ab5456b227..502d5673789 100644
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -306,11 +306,10 @@
     {
       operands[1] = force_reg (<MODE>mode, operands[1]);
 
-      /* For seq-cst stores, use XCHG when we lack MFENCE
-      	 or when target prefers XCHG.  */
+      /* For seq-cst stores, use XCHG when we lack MFENCE.  */
       if (is_mm_seq_cst (model)
 	  && (!(TARGET_64BIT || TARGET_SSE2)
-	      || TARGET_USE_XCHG_FOR_ATOMIC_STORE))
+	      || TARGET_AVOID_MFENCE))
 	{
 	  emit_insn (gen_atomic_exchange<mode> (gen_reg_rtx (<MODE>mode),
 						operands[0], operands[1],
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index 1776aba2d17..6eff8256897 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -313,8 +313,8 @@ DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
 	  m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
 	  | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)
 
-/* X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE: Use xchg instead of mov+mfence.  */
-DEF_TUNE (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE, "use_xchg_for_atomic_store",
+/* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence.  */
+DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
 	 m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC)
 
 /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by