[gcc(refs/vendors/ARM/heads/arm-perf-staging)] i386: Remove %q modifier from two pmov insn templates [PR95355]

[Tamar Christina]

https://gcc.gnu.org/g:31d827e98ab32060ef522fa5f3e42c1175e1a439

commit 31d827e98ab32060ef522fa5f3e42c1175e1a439
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Thu May 28 13:56:54 2020 +0200

    i386: Remove %q modifier from two pmov insn templates [PR95355]
    
    2020-05-28  Uroš Bizjak  <ubizjak@gmail.com>
    
    gcc/ChangeLog:
            PR target/95355
            * config/i386/sse.md
            (<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>):
            Remove %q operand modifier from insn template.
            (avx512f_<code>v8hiv8di2<mask_name>): Ditto.
    
    gcc/testsuite/ChangeLog:
            PR target/95355
            * gcc.target/i386/pr95355.c: New test.

Diff:
---
 gcc/config/i386/sse.md                  |  4 ++--
 gcc/testsuite/gcc.target/i386/pr95355.c | 20 ++++++++++++++++++++
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 90ced8599ca..ad798121bc4 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -17457,7 +17457,7 @@
 	(any_extend:V16SI
 	  (match_operand:V16QI 1 "nonimmediate_operand" "vm")))]
   "TARGET_AVX512F"
-  "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
+  "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix" "evex")
    (set_attr "mode" "XI")])
@@ -17734,7 +17734,7 @@
 	(any_extend:V8DI
 	  (match_operand:V8HI 1 "nonimmediate_operand" "vm")))]
   "TARGET_AVX512F"
-  "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}"
+  "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix" "evex")
    (set_attr "mode" "XI")])
diff --git a/gcc/testsuite/gcc.target/i386/pr95355.c b/gcc/testsuite/gcc.target/i386/pr95355.c
new file mode 100644
index 00000000000..3e4faba19f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95355.c
@@ -0,0 +1,20 @@
+/* PR target/95355 */
+/* { dg-do assemble { target avx512dq } } */
+/* { dg-require-effective-target int128 } */
+/* { dg-require-effective-target masm_intel } */
+/* { dg-options "-O -fno-tree-dominator-opts -fno-tree-fre -ftree-slp-vectorize -fno-tree-ter -mavx512dq -masm=intel" } */
+
+typedef int __attribute__((__vector_size__(64))) U;
+typedef __int128 __attribute__((__vector_size__(32))) V;
+
+U i;
+V j;
+
+int
+foo(unsigned char l)
+{
+  V m = j % 999;
+  U n = l <= i;
+  V o = ((union { U a; V b[2]; }) n).b[0] + m;
+  return o[0];
+}