[gcc(refs/vendors/ARM/heads/arm-perf-staging)] amdgcn: Split 64-bit constant loads post-reload

[Tamar Christina]

https://gcc.gnu.org/g:01f5d5e8f9bc4df0b99dd5b825b39e10af543304

commit 01f5d5e8f9bc4df0b99dd5b825b39e10af543304
Author: Andrew Stubbs <ams@codesourcery.com>
Date:   Thu Mar 19 17:43:12 2020 +0000

    amdgcn: Split 64-bit constant loads post-reload
    
    This helps avoid spilling 64-bit constant loads to stack by simplifying the
    code that LRA sees.
    
    2020-04-24  Andrew Stubbs  <ams@codesourcery.com>
    
            gcc/
            * config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.

Diff:
---
 gcc/ChangeLog         | 4 ++++
 gcc/config/gcn/gcn.md | 8 +++++---
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d402ae643d3..2db3413a973 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2020-04-24  Andrew Stubbs  <ams@codesourcery.com>
+
+	* config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
+
 2020-04-24  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* config/aarch64/arm_sve.h: Add a comment.
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index 702ba55c11a..8f5937781b2 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -615,9 +615,11 @@
   ds_read_b64\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
   global_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
   global_store_dwordx2\t%A0, %1%O0%g0"
-  "(reload_completed && !MEM_P (operands[0]) && !MEM_P (operands[1])
-    && !gcn_sgpr_move_p (operands[0], operands[1]))
-   || (GET_CODE (operands[1]) == CONST_INT && !gcn_constant64_p (operands[1]))"
+  "reload_completed
+   && ((!MEM_P (operands[0]) && !MEM_P (operands[1])
+        && !gcn_sgpr_move_p (operands[0], operands[1]))
+       || (GET_CODE (operands[1]) == CONST_INT
+	   && !gcn_constant64_p (operands[1])))"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2) (match_dup 3))]
   {