[gcc(refs/vendors/ARM/heads/arm-perf-staging)] arm: MVE: Fix constant load pattern
Tamar Christina
tnfchris@gcc.gnu.org
Fri Jul 17 14:26:02 GMT 2020
https://gcc.gnu.org/g:b094133c1c5bf21ccd60c344de6f4a798140e61b
commit b094133c1c5bf21ccd60c344de6f4a798140e61b
Author: Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com>
Date: Tue Apr 7 13:36:43 2020 +0100
arm: MVE: Fix constant load pattern
This patch fixes the constant load pattern for MVE, this was not accounting
correctly for label + offset cases.
Added test that ICE'd before and removed the scan assemblers for the mve_vector*
tests as they were too fragile.
gcc/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm.c (output_move_neon): Deal with label + offset cases.
* config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
gcc/testsuite/ChangeLog:
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/mve/intrinsics/mve_load_from_array.c: New test.
* gcc.target/arm/mve/intrinsics/mve_vector_float.c: Remove
scan-assembler.
* gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
* gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.
Diff:
---
gcc/ChangeLog | 5 ++
gcc/config/arm/arm.c | 55 +++++++++-------------
gcc/config/arm/mve.md | 6 +--
gcc/testsuite/ChangeLog | 9 ++++
.../arm/mve/intrinsics/mve_load_from_array.c | 19 ++++++++
.../arm/mve/intrinsics/mve_vector_float.c | 8 ----
.../arm/mve/intrinsics/mve_vector_float1.c | 8 ----
.../arm/mve/intrinsics/mve_vector_int1.c | 15 ------
.../arm/mve/intrinsics/mve_vector_int2.c | 16 -------
9 files changed, 59 insertions(+), 82 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9d089cbf85d..b76a51a3758 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/arm/arm.c (output_move_neon): Deal with label + offset cases.
+ * config/arm/mve.md (*mve_mov<mode>): Handle const vectors.
+
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/arm/arm_mve.h: Remove use of typeof for addr pointer parameters
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index d5207e0d8f0..1af9d5cf145 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -20122,52 +20122,43 @@ output_move_neon (rtx *operands)
break;
}
/* Fall through. */
- case LABEL_REF:
case PLUS:
+ addr = XEXP (addr, 0);
+ /* Fall through. */
+ case LABEL_REF:
{
int i;
int overlap = -1;
- if (TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN
- && GET_CODE (addr) != LABEL_REF)
+ for (i = 0; i < nregs; i++)
{
- sprintf (buff, "v%srw.32\t%%q0, %%1", load ? "ld" : "st");
- ops[0] = reg;
- ops[1] = mem;
- output_asm_insn (buff, ops);
- }
- else
- {
- for (i = 0; i < nregs; i++)
+ /* We're only using DImode here because it's a convenient
+ size. */
+ ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i);
+ ops[1] = adjust_address (mem, DImode, 8 * i);
+ if (reg_overlap_mentioned_p (ops[0], mem))
{
- /* We're only using DImode here because it's a convenient
- size. */
- ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * i);
- ops[1] = adjust_address (mem, DImode, 8 * i);
- if (reg_overlap_mentioned_p (ops[0], mem))
- {
- gcc_assert (overlap == -1);
- overlap = i;
- }
- else
- {
- if (TARGET_HAVE_MVE && GET_CODE (addr) == LABEL_REF)
- sprintf (buff, "v%sr.64\t%%P0, %%1", load ? "ld" : "st");
- else
- sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
- output_asm_insn (buff, ops);
- }
+ gcc_assert (overlap == -1);
+ overlap = i;
}
- if (overlap != -1)
+ else
{
- ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap);
- ops[1] = adjust_address (mem, SImode, 8 * overlap);
if (TARGET_HAVE_MVE && GET_CODE (addr) == LABEL_REF)
- sprintf (buff, "v%sr.32\t%%P0, %%1", load ? "ld" : "st");
+ sprintf (buff, "v%sr.64\t%%P0, %%1", load ? "ld" : "st");
else
sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
output_asm_insn (buff, ops);
}
}
+ if (overlap != -1)
+ {
+ ops[0] = gen_rtx_REG (DImode, REGNO (reg) + 2 * overlap);
+ ops[1] = adjust_address (mem, SImode, 8 * overlap);
+ if (TARGET_HAVE_MVE && GET_CODE (addr) == LABEL_REF)
+ sprintf (buff, "v%sr.32\t%%P0, %%1", load ? "ld" : "st");
+ else
+ sprintf (buff, "v%sr%%?\t%%P0, %%1", load ? "ld" : "st");
+ output_asm_insn (buff, ops);
+ }
return "";
}
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index d1028f4542b..10abc3fae37 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -695,9 +695,9 @@
case 2:
return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
case 4:
- if ((TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))
- || (MEM_P (operands[1])
- && GET_CODE (XEXP (operands[1], 0)) == LABEL_REF))
+ if (MEM_P (operands[1])
+ && (GET_CODE (XEXP (operands[1], 0)) == LABEL_REF
+ || GET_CODE (XEXP (operands[1], 0)) == CONST))
return output_move_neon (operands);
else
return "vldrb.8 %q0, %E1";
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5a00c47efb4..3f3cf24c8a9 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * gcc.target/arm/mve/intrinsics/mve_load_from_array.c: New test.
+ * gcc.target/arm/mve/intrinsics/mve_vector_float.c: Remove
+ scan-assembler.
+ * gcc.target/arm/mve/intrinsics/mve_vector_float1.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/mve_vector_int1.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/mve_vector_int2.c: Likewise.
+
2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
* gcc.target/arm/mve/intrinsics/vmulq_n_f16.c: Fix test.
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_load_from_array.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_load_from_array.c
new file mode 100644
index 00000000000..dcf6225a98f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_load_from_array.c
@@ -0,0 +1,19 @@
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+uint16x8_t
+foo (void)
+{
+ static uint16_t const a[] = {0, 1, 2, 3, 4, 5, 6, 7};
+ return vld1q (a);
+}
+
+uint16_t b[] = {0, 1, 2, 3, 4, 5, 6, 7};
+void
+bar (uint16x8_t value)
+{
+ vst1q (b, value);
+}
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c
index 9de47e6a1e0..881157fc1be 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float.c
@@ -11,17 +11,9 @@ foo32 (float32x4_t value)
return b;
}
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldmia.*" } } */
-
float16x8_t
foo16 (float16x8_t value)
{
float16x8_t b = value;
return b;
}
-
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldmia.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c
index ba8fb6dd5da..9515ed622ac 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_float1.c
@@ -13,10 +13,6 @@ foo32 ()
return b;
}
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldmia.*" } } */
-
float16x8_t value1;
float16x8_t
@@ -25,7 +21,3 @@ foo16 ()
float16x8_t b = value1;
return b;
}
-
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldmia.*" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c
index 2d2fd116dfc..e54516b2530 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int1.c
@@ -16,10 +16,6 @@ foo8 (void)
return b;
}
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldrb.8*" } } */
-
int16x8_t
foo16 (void)
{
@@ -27,10 +23,6 @@ foo16 (void)
return b;
}
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldrb.8*" } } */
-
int32x4_t
foo32 (void)
{
@@ -38,10 +30,6 @@ foo32 (void)
return b;
}
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldrb.8" } } */
-
int64x2_t
foo64 (void)
{
@@ -49,6 +37,3 @@ foo64 (void)
return b;
}
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldrb.8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c
index 7ec85866993..2bd9bdfed92 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_vector_int2.c
@@ -11,10 +11,6 @@ foo8 ()
return b;
}
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldr.64.*" } } */
-
int16x8_t
foo16 (int16x8_t value)
{
@@ -22,10 +18,6 @@ foo16 (int16x8_t value)
return b;
}
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldr.64.*" } } */
-
int32x4_t
foo32 (int32x4_t value)
{
@@ -33,17 +25,9 @@ foo32 (int32x4_t value)
return b;
}
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldr.64.*" } } */
-
int64x2_t
foo64 (int64x2_t value)
{
int64x2_t b = {1};
return b;
}
-
-/* { dg-final { scan-assembler "vmov\\tq\[0-7\], q\[0-7\]" } } */
-/* { dg-final { scan-assembler "vstrb.*" } } */
-/* { dg-final { scan-assembler "vldr.64.*" } } */
More information about the Gcc-cvs
mailing list