[gcc(refs/vendors/ARM/heads/arm-struct-reorg-wip)] i386: Skip ENDBR32 at the target function entry

[Tamar Christina]

https://gcc.gnu.org/g:1d69147af203d4dcd2270429f90c93f1a37ddfff

commit 1d69147af203d4dcd2270429f90c93f1a37ddfff
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Thu Feb 13 05:28:38 2020 -0800

    i386: Skip ENDBR32 at the target function entry
    
    Skip ENDBR32 at the target function entry when initializing trampoline.
    
    Tested on Linux/x86-64 CET machine with and without -m32.
    
    gcc/
    
            PR target/93656
            * config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
            the target function entry.
    
    gcc/testsuite/
    
            PR target/93656
            * gcc.target/i386/pr93656.c: New test.

Diff:
---
 gcc/ChangeLog                           | 6 ++++++
 gcc/config/i386/i386.c                  | 7 ++++++-
 gcc/testsuite/ChangeLog                 | 5 +++++
 gcc/testsuite/gcc.target/i386/pr93656.c | 4 ++++
 4 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 41498390c21..d9fb2c81e0e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-02-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/93656
+	* config/i386/i386.c (ix86_trampoline_init): Skip ENDBR32 at
+	the target function entry.
+
 2020-02-13  Claudiu Zissulescu  <claziss@synopsys.com>
 
 	* common/config/arc/arc-common.c (arc_option_optimization_table):
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 44bc0e0176a..dac7a3fc5fd 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -16839,9 +16839,14 @@ ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
 	 the stack, we need to skip the first insn which pushes the
 	 (call-saved) register static chain; this push is 1 byte.  */
       offset += 5;
+      int skip = MEM_P (chain) ? 1 : 0;
+      /* Skip ENDBR32 at the entry of the target function.  */
+      if (need_endbr
+	  && !cgraph_node::get (fndecl)->only_called_directly_p ())
+	skip += 4;
       disp = expand_binop (SImode, sub_optab, fnaddr,
 			   plus_constant (Pmode, XEXP (m_tramp, 0),
-					  offset - (MEM_P (chain) ? 1 : 0)),
+					  offset - skip),
 			   NULL_RTX, 1, OPTAB_DIRECT);
       emit_move_insn (mem, disp);
     }
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5ac858efb1b..c296fc38109 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/93656
+	* gcc.target/i386/pr93656.c: New test.
+
 2020-02-13  Claudiu Zissulescu  <claziss@synopsys.com>
 
 	* gcc.target/arc/nps400-1.c: Update test.
diff --git a/gcc/testsuite/gcc.target/i386/pr93656.c b/gcc/testsuite/gcc.target/i386/pr93656.c
new file mode 100644
index 00000000000..f0ac8c8edaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr93656.c
@@ -0,0 +1,4 @@
+/* { dg-do run { target { ia32 && cet } } } */
+/* { dg-options "-O2 -fcf-protection" } */
+
+#include "pr67770.c"