[gcc/devel/gccgo] i386: Add V2DFmode conversion functions [PR95046]
Ian Lance Taylor
ian@gcc.gnu.org
Sun Jul 12 18:15:59 GMT 2020
https://gcc.gnu.org/g:365e3cde4978c6a7dbfa50865720226254c016be
commit 365e3cde4978c6a7dbfa50865720226254c016be
Author: Uros Bizjak <ubizjak@gmail.com>
Date: Thu May 14 13:47:33 2020 +0200
i386: Add V2DFmode conversion functions [PR95046]
gcc/ChangeLog:
PR target/95046
* config/i386/sse.md (sse2_cvtpi2pd): Add memory to alternative 1.
(floatv2siv2df2): New expander.
(floatunsv2siv2df2): New insn pattern.
(fix_truncv2dfv2si2): New expander.
(fixuns_truncv2dfv2si2): New insn pattern.
testsuite/ChangeLog:
PR target/95046
* gcc.target/i386/pr95046-6.c: New test.
Diff:
---
gcc/ChangeLog | 19 ++++++++++---
gcc/config/i386/sse.md | 34 ++++++++++++++++++++++--
gcc/testsuite/ChangeLog | 5 ++++
gcc/testsuite/gcc.target/i386/pr95046-6.c | 44 +++++++++++++++++++++++++++++++
4 files changed, 96 insertions(+), 6 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 125f7c7c389..072ad082852 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * config/i386/sse.md (sse2_cvtpi2pd): Add memory to alternative 1.
+
+ (floatv2siv2df2): New expander.
+ (floatunsv2siv2df2): New insn pattern.
+
+ (fix_truncv2dfv2si2): New expander.
+ (fixuns_truncv2dfv2si2): New insn pattern.
+
2020-05-14 Richard Sandiford <richard.sandiford@arm.com>
PR target/95105
@@ -37,7 +48,7 @@
cfun->curr_properties has PROP_gimple_any bit set.
(struct omp_declare_variant_entry): New type.
(struct omp_declare_variant_base_entry): New type.
- (struct omp_declare_variant_hasher): New type.
+ (struct omp_declare_variant_hasher): New type.
(omp_declare_variant_hasher::hash, omp_declare_variant_hasher::equal):
New methods.
(omp_declare_variants): New variable.
@@ -75,19 +86,19 @@
2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
PR target/95046
- * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): rename from mmx_pf2id.
+ * config/i386/mmx.md (mmx_fix_truncv2sfv2si2): Rename from mmx_pf2id.
Add SSE/AVX alternative. Change operand predicates from
nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(fix_truncv2sfv2si2): New expander.
- (fixuns_truncv2sfv2si2): Ditto.
+ (fixuns_truncv2sfv2si2): New insn pattern.
(mmx_floatv2siv2sf2): rename from mmx_floatv2si2.
Add SSE/AVX alternative. Change operand predicates from
nonimmediate_operand to register_mmxmem_operand.
Enable instruction pattern for TARGET_MMX_WITH_SSE.
(floatv2siv2sf2): New expander.
- (floatunsv2siv2sf2): Ditto.
+ (floatunsv2siv2sf2): New insn pattern.
* config/i386/i386-builtin.def (IX86_BUILTIN_PF2ID):
Update for rename.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 7a7ecd4be87..dc0ecbc182e 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -5532,8 +5532,8 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn "sse2_cvtpi2pd"
- [(set (match_operand:V2DF 0 "register_operand" "=v,x")
- (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "vBm,?!y")))]
+ [(set (match_operand:V2DF 0 "register_operand" "=v,?!x")
+ (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "vBm,yBm")))]
"TARGET_SSE2"
"@
%vcvtdq2pd\t{%1, %0|%0, %1}
@@ -5545,6 +5545,21 @@
(set_attr "prefix" "maybe_vex,*")
(set_attr "mode" "V2DF")])
+(define_expand "floatv2siv2df2"
+ [(set (match_operand:V2DF 0 "register_operand")
+ (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand")))]
+ "TARGET_MMX_WITH_SSE")
+
+(define_insn "floatunsv2siv2df2"
+ [(set (match_operand:V2DF 0 "register_operand" "=v")
+ (unsigned_float:V2DF
+ (match_operand:V2SI 1 "nonimmediate_operand" "vm")))]
+ "TARGET_MMX_WITH_SSE && TARGET_AVX512VL"
+ "vcvtudq2pd\t{%1, %0|%0, %1}"
+ [(set_attr "type" "ssecvt")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "V2DF")])
+
(define_insn "sse2_cvtpd2pi"
[(set (match_operand:V2SI 0 "register_operand" "=v,?!y")
(unspec:V2SI [(match_operand:V2DF 1 "vector_operand" "vBm,xBm")]
@@ -5580,6 +5595,21 @@
(set_attr "prefix" "maybe_vex,*")
(set_attr "mode" "TI")])
+(define_expand "fix_truncv2dfv2si2"
+ [(set (match_operand:V2SI 0 "register_operand")
+ (fix:V2SI (match_operand:V2DF 1 "vector_operand")))]
+ "TARGET_MMX_WITH_SSE")
+
+(define_insn "fixuns_truncv2dfv2si2"
+ [(set (match_operand:V2SI 0 "register_operand" "=v")
+ (unsigned_fix:V2SI
+ (match_operand:V2DF 1 "nonimmediate_operand" "vm")))]
+ "TARGET_MMX_WITH_SSE && TARGET_AVX512VL"
+ "vcvttpd2udq{x}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "ssecvt")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "TI")])
+
(define_insn "sse2_cvtsi2sd"
[(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
(vec_merge:V2DF
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5163470c245..e1694682999 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-05-14 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/95046
+ * gcc.target/i386/pr95046-6.c: New test.
+
2020-05-14 Richard Sandiford <richard.sandiford@arm.com>
PR target/95105
diff --git a/gcc/testsuite/gcc.target/i386/pr95046-6.c b/gcc/testsuite/gcc.target/i386/pr95046-6.c
new file mode 100644
index 00000000000..dcc8999c446
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95046-6.c
@@ -0,0 +1,44 @@
+/* PR target/95046 */
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O3 -mavx512vl" } */
+
+
+double r[2];
+int s[2];
+unsigned int u[2];
+
+void
+test_float (void)
+{
+ for (int i = 0; i < 2; i++)
+ r[i] = s[i];
+}
+
+/* { dg-final { scan-assembler "\tvcvtdq2pd" } } */
+
+void
+test_ufloat (void)
+{
+ for (int i = 0; i < 2; i++)
+ r[i] = u[i];
+}
+
+/* { dg-final { scan-assembler "\tvcvtudq2pd" } } */
+
+void
+test_fix (void)
+{
+ for (int i = 0; i < 2; i++)
+ s[i] = r[i];
+}
+
+/* { dg-final { scan-assembler "\tvcvttpd2dqx" } } */
+
+void
+test_ufix (void)
+{
+ for (int i = 0; i < 2; i++)
+ u[i] = r[i];
+}
+
+/* { dg-final { scan-assembler "\tvcvttpd2udqx" } } */
More information about the Gcc-cvs
mailing list