[gcc(refs/vendors/redhat/heads/gcc-9-branch)] [ARC] Enable using DCMPF for hard float comparisons (backports)
Jakub Jelinek
jakub@gcc.gnu.org
Wed Jan 22 20:20:00 GMT 2020
https://gcc.gnu.org/g:e757124bc3644d491ff2e5fa93580debf097c984
commit e757124bc3644d491ff2e5fa93580debf097c984
Author: Claudiu Zissulescu <claziss@gcc.gnu.org>
Date: Thu Dec 12 10:31:56 2019 +0100
[ARC] Enable using DCMPF for hard float comparisons (backports)
Diff:
---
gcc/ChangeLog | 19 +++++++++++++++++++
gcc/config/arc/arc-modes.def | 1 +
gcc/config/arc/arc.c | 8 ++++++--
gcc/config/arc/arc.h | 2 +-
gcc/config/arc/arc.md | 4 ++--
gcc/config/arc/fpu.md | 24 ++++++++++++++++++++++++
gcc/config/arc/predicates.md | 1 +
7 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9edb346..3845274 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2019-12-12 Vineet Gupta <vgupta@synopsys.com>
+
+ Backport from mainline
+ * config/arc/arc-modes.def (CC_FPUE): New Mode CC_FPUE which
+ helps codegen generate exceptions even for quiet NaN.
+ * config/arc/arc.c (arc_init_reg_tables): Handle New CC_FPUE mode.
+ (get_arc_condition_code): Likewise.
+ (arc_select_cc_mode): LT, LE, GT, GE to use the New CC_FPUE mode.
+ * config/arc/arc.h (REVERSE_CONDITION): Handle New CC_FPUE mode.
+ * config/arc/predicates.md (proper_comparison_operator): Likewise.
+ * config/arc/fpu.md (cmpsf_fpu_trap): New Pattern for CC_FPUE.
+ (cmpdf_fpu_trap): Likewise.
+
+2019-12-12 Claudiu Zissulescu <claziss@synopsys.com>
+
+ Backport from mainline
+ * config/arc/arc.md (iterator SDF): Check TARGET_FP_DP_BASE.
+ (cstoredi4): Use TARGET_HARD_FLOAT.
+
2019-12-10 Kewen Lin <linkw@gcc.gnu.org>
Backport from mainline
diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def
index 36a2f4a..d16b6a2 100644
--- a/gcc/config/arc/arc-modes.def
+++ b/gcc/config/arc/arc-modes.def
@@ -38,4 +38,5 @@ VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
/* FPU condition flags. */
CC_MODE (CC_FPU);
+CC_MODE (CC_FPUE);
CC_MODE (CC_FPU_UNEQ);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index e6e4fb1..f7ff95a 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1445,6 +1445,7 @@ get_arc_condition_code (rtx comparison)
default : gcc_unreachable ();
}
case E_CC_FPUmode:
+ case E_CC_FPUEmode:
switch (GET_CODE (comparison))
{
case EQ : return ARC_CC_EQ;
@@ -1567,11 +1568,13 @@ arc_select_cc_mode (enum rtx_code op, rtx x, rtx y)
case UNLE:
case UNGT:
case UNGE:
+ return CC_FPUmode;
+
case LT:
case LE:
case GT:
case GE:
- return CC_FPUmode;
+ return CC_FPUEmode;
case LTGT:
case UNEQ:
@@ -1725,7 +1728,7 @@ arc_init_reg_tables (void)
if (i == (int) CCmode || i == (int) CC_ZNmode || i == (int) CC_Zmode
|| i == (int) CC_Cmode
|| i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode
- || i == CC_FPUmode || i == CC_FPU_UNEQmode)
+ || i == CC_FPUmode || i == CC_FPUEmode || i == CC_FPU_UNEQmode)
arc_mode_class[i] = 1 << (int) C_MODE;
else
arc_mode_class[i] = 0;
@@ -8233,6 +8236,7 @@ arc_reorg (void)
/* Avoid FPU instructions. */
if ((GET_MODE (XEXP (XEXP (pc_target, 0), 0)) == CC_FPUmode)
+ || (GET_MODE (XEXP (XEXP (pc_target, 0), 0)) == CC_FPUEmode)
|| (GET_MODE (XEXP (XEXP (pc_target, 0), 0)) == CC_FPU_UNEQmode))
continue;
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 80dead9..00fc3e4 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1530,7 +1530,7 @@ enum arc_function_type {
(((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \
|| (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \
|| (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \
- || (MODE) == CC_FPUmode) \
+ || (MODE) == CC_FPUmode || (MODE) == CC_FPUEmode) \
? reverse_condition_maybe_unordered ((CODE)) \
: reverse_condition ((CODE)))
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 722cccd..34e8248 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -3674,7 +3674,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
})
(define_mode_iterator SDF [(SF "TARGET_FP_SP_BASE || TARGET_OPTFPE")
- (DF "TARGET_OPTFPE")])
+ (DF "TARGET_FP_DP_BASE || TARGET_OPTFPE")])
(define_expand "cstore<mode>4"
[(set (reg:CC CC_REG)
@@ -3684,7 +3684,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
(match_operator:SI 1 "comparison_operator" [(reg CC_REG)
(const_int 0)]))]
- "TARGET_FP_SP_BASE || TARGET_OPTFPE"
+ "TARGET_HARD_FLOAT || TARGET_OPTFPE"
{
gcc_assert (XEXP (operands[1], 0) == operands[2]);
gcc_assert (XEXP (operands[1], 1) == operands[3]);
diff --git a/gcc/config/arc/fpu.md b/gcc/config/arc/fpu.md
index 6289e9c..6729795 100644
--- a/gcc/config/arc/fpu.md
+++ b/gcc/config/arc/fpu.md
@@ -242,6 +242,18 @@
(set_attr "type" "fpu")
(set_attr "predicable" "yes")])
+(define_insn "*cmpsf_fpu_trap"
+ [(set (reg:CC_FPUE CC_REG)
+ (compare:CC_FPUE (match_operand:SF 0 "register_operand" "r, r,r")
+ (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))]
+ "TARGET_FP_SP_BASE"
+ "fscmpf%?\\t%0,%1"
+ [(set_attr "length" "4,4,8")
+ (set_attr "iscompact" "false")
+ (set_attr "cond" "set")
+ (set_attr "type" "fpu")
+ (set_attr "predicable" "yes")])
+
(define_insn "*cmpsf_fpu_uneq"
[(set (reg:CC_FPU_UNEQ CC_REG)
(compare:CC_FPU_UNEQ
@@ -338,6 +350,18 @@
(set_attr "type" "fpu")
(set_attr "predicable" "yes")])
+(define_insn "*cmpdf_fpu_trap"
+ [(set (reg:CC_FPUE CC_REG)
+ (compare:CC_FPUE (match_operand:DF 0 "even_register_operand" "r")
+ (match_operand:DF 1 "even_register_operand" "r")))]
+ "TARGET_FP_DP_BASE"
+ "fdcmpf%? %0, %1"
+ [(set_attr "length" "4")
+ (set_attr "iscompact" "false")
+ (set_attr "cond" "set")
+ (set_attr "type" "fpu")
+ (set_attr "predicable" "yes")])
+
(define_insn "*cmpdf_fpu_uneq"
[(set (reg:CC_FPU_UNEQ CC_REG)
(compare:CC_FPU_UNEQ
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index 72fbf2a..7d31ad9 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -437,6 +437,7 @@
|| code == ORDERED || code == UNORDERED);
case E_CC_FPUmode:
+ case E_CC_FPUEmode:
return 1;
case E_CC_FPU_UNEQmode:
return 1;
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