[gcc(refs/users/meissner/heads/work011)] PowerPC: Add power10 IEEE 128-bit min and max built-ins.

[Michael Meissner]

https://gcc.gnu.org/g:5af00200ea3b359959c5f73211a01b7b81812032

commit 5af00200ea3b359959c5f73211a01b7b81812032
Author: Michael Meissner <meissner@gcc.gnu.org>
Date:   Tue Aug 18 17:20:52 2020 -0400

    PowerPC: Add power10 IEEE 128-bit min and max built-ins.
    
    gcc/
    2020-08-18  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/rs6000.h (FLOAT128_IEEE_MINMAX_P): New helper
            macro.
            * config/rs6000/rs6000.md (FMIN): New mode iterator for floating
            point min/max.
            (Fm): New mode attribute for floating point min/max.
            (s<minmax><mode>): Add support for the ISA 3.1 IEEE 128-bit
            minimum and maximum instructions.
            (s<minmax><mode>3_vsx): Add support for the ISA 3.1 IEEE 128-bit
            minimum and maximum instructions.
    
    gcc/testsuite/
    2020-08-18  Michael Meissner  <meissner@linux.ibm.com>
    
            * gcc.target/powerpc/float128-minmax-2.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000.c                         |  3 ++-
 gcc/config/rs6000/rs6000.h                         |  4 ++++
 gcc/config/rs6000/rs6000.md                        | 27 +++++++++++++++++-----
 .../gcc.target/powerpc/float128-minmax-2.c         | 15 ++++++++++++
 4 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 425df2dfbdf..a6bf158c46e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15461,7 +15461,8 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
   /* VSX/altivec have direct min/max insns.  */
   if ((code == SMAX || code == SMIN)
       && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
-	  || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
+	  || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))
+	  || FLOAT128_IEEE_MINMAX_P (mode)))
     {
       emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
       return;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index bbd8060e143..b504aaa0199 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -345,6 +345,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
    || ((MODE) == TDmode)						\
    || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
 
+/* Macro whether the float128 min/max instructions are enabled.  */
+#define FLOAT128_IEEE_MINMAX_P(MODE)					\
+  (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (MODE))
+
 /* Return true for floating point that does not use a vector register.  */
 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE)				\
   (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index d9dd25f5715..3d8b287d9d9 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -797,6 +797,18 @@
 (define_code_attr     SMINMAX	[(smin "SMIN")
 				 (smax "SMAX")])
 
+;; Mode iterator for floating point min/max
+(define_mode_iterator FMIN [SF
+			    DF
+			    (KF "FLOAT128_IEEE_MINMAX_P (KFmode)")
+			    (TF "FLOAT128_IEEE_MINMAX_P (KFmode)")])
+
+;; Constraints to use for min/max operations.
+(define_mode_attr Fm [(SF "wa")
+		      (DF "wa")
+		      (TF "v")
+		      (KF "v")])
+
 ;; Iterator to optimize the following cases:
 ;;	D-form load to FPR register & move to Altivec register
 ;;	Move Altivec register to FPR register and store
@@ -5150,9 +5162,9 @@
 ;; to allow either DF/SF to use only traditional registers.
 
 (define_expand "s<minmax><mode>3"
-  [(set (match_operand:SFDF 0 "gpc_reg_operand")
-	(fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand")
-			(match_operand:SFDF 2 "gpc_reg_operand")))]
+  [(set (match_operand:FMIN 0 "gpc_reg_operand")
+	(fp_minmax:FMIN (match_operand:FMIN 1 "gpc_reg_operand")
+			(match_operand:FMIN 2 "gpc_reg_operand")))]
   "TARGET_MINMAX"
 {
   rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]);
@@ -5160,11 +5172,14 @@
 })
 
 (define_insn "*s<minmax><mode>3_vsx"
-  [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
-	(fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "<Fv>")
-			(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")))]
+  [(set (match_operand:FMIN 0 "vsx_register_operand" "=<Fm>")
+	(fp_minmax:FMIN (match_operand:FMIN 1 "vsx_register_operand" "<Fm>")
+			(match_operand:FMIN 2 "vsx_register_operand" "<Fm>")))]
   "TARGET_VSX && TARGET_HARD_FLOAT"
 {
+  if (FLOAT128_IEEE_P (<MODE>mode))
+    return "xs<minmax>cdp %0,%1,%2";
+
   return (TARGET_P9_MINMAX
 	  ? "xs<minmax>cdp %x0,%x1,%x2"
 	  : "xs<minmax>dp %x0,%x1,%x2");
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
new file mode 100644
index 00000000000..76ba5f67e47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c
@@ -0,0 +1,15 @@
+/* { dg-require-effective-target powerpc_float128_hw_ok } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */
+
+#ifndef TYPE
+#define TYPE _Float128
+#endif
+
+/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a
+   call.  */
+TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); }
+TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); }
+
+/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */
+/* { dg-final { scan-assembler {\mxsmincqp\M} } } */