[gcc(refs/users/guojiufu/heads/personal-branch)] aarch64: Add support for unpacked sub [PR96366]
Jiu Fu Guo
guojiufu@gcc.gnu.org
Mon Aug 10 07:36:16 GMT 2020
https://gcc.gnu.org/g:9623f61b142174b87760c81f78928dd14af7cbc6
commit 9623f61b142174b87760c81f78928dd14af7cbc6
Author: Bu Le <bule1@huawei.com>
Date: Mon Aug 3 16:38:46 2020 +0100
aarch64: Add support for unpacked sub [PR96366]
The test case bb-slp-20.c in the gcc testsuit will cause an
ICE in the expand pass due to the lack of a pattern for
subtraction of the VNx2SI mode. This patch solve this problem
by adding support for unpacked sub.
gcc/ChangeLog:
* config/aarch64/aarch64-sve.md (sub<mode>3): Add support for
unpacked vectors.
Diff:
---
gcc/config/aarch64/aarch64-sve.md | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 9d06bf719b5..182813c1c5c 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -3644,10 +3644,10 @@
;; -------------------------------------------------------------------------
(define_insn "sub<mode>3"
- [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, ?&w")
- (minus:SVE_FULL_I
- (match_operand:SVE_FULL_I 1 "aarch64_sve_arith_operand" "w, vsa, vsa")
- (match_operand:SVE_FULL_I 2 "register_operand" "w, 0, w")))]
+ [(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w")
+ (minus:SVE_I
+ (match_operand:SVE_I 1 "aarch64_sve_arith_operand" "w, vsa, vsa")
+ (match_operand:SVE_I 2 "register_operand" "w, 0, w")))]
"TARGET_SVE"
"@
sub\t%0.<Vetype>, %1.<Vetype>, %2.<Vetype>
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