r252123 - in /branches/range-gen2/gcc: ChangeLo...

[aldyh@gcc.gnu.org]

Author: aldyh
Date: Wed Sep 13 15:53:36 2017
New Revision: 252123

URL: https://gcc.gnu.org/viewcvs?rev=252123&root=gcc&view=rev
Log:
[PATCH][AArch64] Fix missing optimization for CMP+AND

During combine GCC tries to merge CMP (with zero) and AND into a TST. However,
in cases where an ANDS operand is not compatible, this was being missed. Adding
a define_split where this operand was moved to a register seems to help out. 

Committed on behalf of Sudi Das

---
gcc/

2017-07-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* config/aarch64/aarch64.md
	(define_split for and<mode>3nr_compare): Move
	non aarch64_logical_operand to a register.
	(define_split for and_<SHIFT:optab><mode>3nr_compare0): Move non
	register immediate operand to a register.
	* config/aarch64/predicates.md (aarch64_mov_imm_operand): New.

gcc/testsuite
    
2017-07-27  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/aarch64/tst_imm_split_1.c: New Test.

Added:
    branches/range-gen2/gcc/testsuite/gcc.target/aarch64/tst_imm_split_1.c
Modified:
    branches/range-gen2/gcc/ChangeLog
    branches/range-gen2/gcc/config/aarch64/aarch64.md
    branches/range-gen2/gcc/config/aarch64/predicates.md
    branches/range-gen2/gcc/testsuite/ChangeLog