r134168 - in /branches/ix86/avx/gcc: ChangeLog....

Thu Apr 10 18:38:00 GMT 2008

Author: hjl
Date: Thu Apr 10 18:38:30 2008
New Revision: 134168

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=134168
Log:
2008-04-10  H.J. Lu  <hongjiu.lu@intel.com>

	* config.gcc (extra_headers): Add gmmintrin.h for x86 and x86-64.

	* config/i386/cpuid.h (bit_FMA): New.
	(bit_XSAVE): Likewise.
	(bit_OSXSAVE): Likewise.
	(bit_AVX): Likewise.

	* config/i386/gmmintrin.h: New.

	* config/i386/i386.c (OPTION_MASK_ISA_AVX_SET): New.
	(OPTION_MASK_ISA_FMA_SET): Likewise.
	(OPTION_MASK_ISA_AVX_UNSET): Likewise.
	(OPTION_MASK_ISA_FMA_SET): Likewise.
	(OPTION_MASK_ISA_SSE4_2_UNSET): Updated.
	(ix86_handle_option): Handle OPT_mavx and OPT_mfma.
	(pta_flags): Add PTA_AVX and PTA_FMA.
	(override_options): Handle PTA_AVX and PTA_FMA.
	(init_cumulative_args): Handle warn_avx.
	(classify_argument): Handle V8SFmode, V8SImode, V32QImode,
	V16HImode, V4DFmode and V4DImode.
	(function_arg_advance_32): Likewise.
	(function_arg_64): Likewise.
	(standard_sse_constant_opcode): Handle AVX modes.
	(print_reg): Handle 'x' and AVX registers.
	(print_operand): Handle 'x' and AVX vector compare instructions.
	(output_387_binary_op): Support AVX.
	(ix86_builtins): Add IX86_BUILTIN_ADDPD256 and
	IX86_BUILTIN_ADDPS256,  IX86_BUILTIN_ADDSUBPD256,
	IX86_BUILTIN_ADDSUBPS256, IX86_BUILTIN_ANDPD256,
	IX86_BUILTIN_ANDPS256, IX86_BUILTIN_ANDNPD256,
	IX86_BUILTIN_ANDNPS256,  IX86_BUILTIN_BLENDPD256,
	IX86_BUILTIN_BLENDPS256, IX86_BUILTIN_BLENDVPD256,
	IX86_BUILTIN_BLENDVPS256, IX86_BUILTIN_DPPS256.
	IX86_BUILTIN_DIVPD256, IX86_BUILTIN_DIVPS256,
	IX86_BUILTIN_HADDPD256, IX86_BUILTIN_HADDPS256,
	IX86_BUILTIN_HSUBPD256, IX86_BUILTIN_HSUBPS256,
	IX86_BUILTIN_MAXPD256, IX86_BUILTIN_MAXPS256,
	IX86_BUILTIN_MINPD256, IX86_BUILTIN_MINPS256,
	IX86_BUILTIN_MULPD256, IX86_BUILTIN_MULPS256,
	IX86_BUILTIN_ORPD256, IX86_BUILTIN_ORPS256,
	IX86_BUILTIN_SHUFPD256, IX86_BUILTIN_SHUFPS256,
	IX86_BUILTIN_SUBPD256, IX86_BUILTIN_SUBPS256,
	IX86_BUILTIN_XORPD256, IX86_BUILTIN_XORPS256,
	IX86_BUILTIN_CMPSD, IX86_BUILTIN_CMPSS, IX86_BUILTIN_CMPPD,
	IX86_BUILTIN_CMPPS, IX86_BUILTIN_CMPPD256, IX86_BUILTIN_CMPPS256,
	IX86_BUILTIN_CVTPD2PS256, IX86_BUILTIN_CVTPS2DQ256,
	IX86_BUILTIN_CVTPS2PD256, IX86_BUILTIN_CVTTPD2DQ256,
	IX86_BUILTIN_CVTPD2DQ256 and IX86_BUILTIN_CVTTPS2DQ256.
	(bdesc_sse_3arg): Add __builtin_ia32_blendpd256,
	__builtin_ia32_blendps256, __builtin_ia32_blendvpd256,
	__builtin_ia32_blendvps256,  __builtin_ia32_dpps256,
	__builtin_ia32_shufpd256, __builtin_ia32_shufps256,
	__builtin_ia32_cmpsd, __builtin_ia32_cmpss,
	__builtin_ia32_cmppd, __builtin_ia32_cmpps,
	__builtin_ia32_cmppd256 and __builtin_ia32_cmpps256.

	(bdesc_2arg): Add __builtin_ia32_addpd256,
	__builtin_ia32_addps256, __builtin_ia32_addsubpd256,
	__builtin_ia32_addsubps256, __builtin_ia32_andpd256,
	__builtin_ia32_andps256, __builtin_ia32_andnpd256,
	__builtin_ia32_andnps256, __builtin_ia32_divpd256,
	__builtin_ia32_divps256, __builtin_ia32_haddpd256,
	__builtin_ia32_hsubps256, __builtin_ia32_hsubpd256,
	__builtin_ia32_haddps256, __builtin_ia32_maxpd256,
	__builtin_ia32_maxps256, __builtin_ia32_minpd256,
	__builtin_ia32_minps256, __builtin_ia32_mulpd256,
	__builtin_ia32_mulps256, __builtin_ia32_orpd256,
	__builtin_ia32_orps256, __builtin_ia32_subpd256,
	__builtin_ia32_subps256, __builtin_ia32_xorpd256,
	__builtin_ia32_xorps256.
	(bdesc_1arg): Add entries for IX86_BUILTIN_CVTDQ2PD256,
	IX86_BUILTIN_CVTDQ2PS256,  IX86_BUILTIN_CVTPD2PS256,
	IX86_BUILTIN_CVTPS2DQ256, IX86_BUILTIN_CVTPS2PD256,
	IX86_BUILTIN_CVTTPD2DQ256, IX86_BUILTIN_CVTPD2DQ256 and
	IX86_BUILTIN_CVTTPS2DQ256.
	(ix86_init_mmx_sse_builtins): Handle __builtin_ia32_blendpd256,
	__builtin_ia32_blendps256, __builtin_ia32_blendvpd256,
	__builtin_ia32_blendvps256, __builtin_ia32_addpd256 and
	__builtin_ia32_addps256.  Define __builtin_ia32_cvtdq2pd256,
	__builtin_ia32_cvtdq2ps256, __builtin_ia32_cvtpd2ps256,
	__builtin_ia32_cvtps2dq256, __builtin_ia32_cvtps2pd256,
	__builtin_ia32_cvttpd2dq256, __builtin_ia32_cvtpd2dq256 and
	__builtin_ia32_cvttps2dq256.
	(ix86_expand_sse_4_operands_builtin): Handle 
	CODE_FOR_avx_blendpd256, CODE_FOR_avx_blendvpd256,
	CODE_FOR_avx_blendvps256, CODE_FOR_avx_cmpsdv2df3,
	CODE_FOR_avx_cmpssv4sf3, CODE_FOR_avx_cmppdv2df3,
	CODE_FOR_avx_cmppsv4sf3, CODE_FOR_avx_cmppsv8sf3 and
	CODE_FOR_avx_cmppdv4df3.
	(ix86_expand_builtin): Use switch instead of if.
	(ix86_hard_regno_mode_ok): Handle AVX mode.
	(ix86_vector_mode_supported_p): Likewise.

	* config/i386/i386.h (TARGET_AVX): New.
	(TARGET_FMA): Likewise.
	(TARGET_CPU_CPP_BUILTINS): Handle TARGET_AVX and TARGET_FMA.
	(BIGGEST_ALIGNMENT): Set to 256 for TARGET_AVX.
	(VALID_AVX_REG_MODE): New.
	(AVX_VEC_FLOAT_MODE_P): Likewise.
	(UNITS_PER_SIMD_WORD): Set to 32 for TARGET_AVX.
	(SSE_REG_MODE_P): Allow AVX modes.
	(ix86_args): Add a warn_avx field.

	* config/i386/i386-modes.def (VECTOR_MODES (INT, 32)): New.
	(VECTOR_MODES (FLOAT, 32)): Likewise.
	(VECTOR_MODE (INT, DI, 8)): Likewise.
	(VECTOR_MODE (INT, HI, 32)): Likewise.
	(VECTOR_MODE (INT, QI, 64)): Likewise.
	(VECTOR_MODE (FLOAT, DF, 8)): Likewise.
	(VECTOR_MODE (FLOAT, SF, 16)): Likewise.
	(VECTOR_MODE (INT, DI, 4)): Removed.
	(VECTOR_MODE (INT, SI, 8)): Likewise.
	(VECTOR_MODE (INT, HI, 16)): Likewise.
	(VECTOR_MODE (INT, QI, 32)): Likewise.
	(VECTOR_MODE (FLOAT, SF, 8)): Likewise.
	(INT_MODE (OI, 32)): Likewise.

	* config/i386/i386.opt (mavx): New.
	(mfma): Likewise.

Added:
    branches/ix86/avx/gcc/config/i386/gmmintrin.h
Modified:
    branches/ix86/avx/gcc/ChangeLog.avx
    branches/ix86/avx/gcc/config.gcc
    branches/ix86/avx/gcc/config/i386/cpuid.h
    branches/ix86/avx/gcc/config/i386/i386-modes.def
    branches/ix86/avx/gcc/config/i386/i386.c
    branches/ix86/avx/gcc/config/i386/i386.h
    branches/ix86/avx/gcc/config/i386/i386.opt