[Bug target/124741] New: Improve RISC-V rvwmo and ztso atomic load/store sequences

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124741

            Bug ID: 124741
           Summary: Improve RISC-V rvwmo and ztso atomic load/store
                    sequences
           Product: gcc
           Version: 16.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: law at gcc dot gnu.org
  Target Milestone: ---

The ztso and rvwmo atomic load/store patterns use the "A" constraint for the
memory operand which forces the address into a register.  There's no real need
for that AFAICT since the emitted code is a standard load/store, potentially
with some fences.

This results in a failure to fold small offsets into the memory address
resulting in silly add instructions in the resulting output.  Here's an example
from jemalloc free() path.  Compile with rv64gc -O2.

.typedef struct
{
  int x;
  unsigned repr;
} atomic_u_t;
unsigned
atomic_load_u (const atomic_u_t *a)
{
  unsigned result;
  __atomic_load (&a->repr, &result, 0);
  return result;
}

It results in this code:

        addi    a5,a0,4
        lw      a0,0(a5)
        sext.w  a0,a0
        ret

The addi should fold in with the lw.  THat can be fixed by using "m" rather
than "A" in the relevant pattern's constraints.

The sext.w is useless as well as the lw already sign extends.  We probably need
an additional pattern for the signed/unsigned extensions.