[Bug target/124736] RISCV: backend generates an invalid vwredsum.vs insn with overlapping register operands

[andrew at sifive dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124736

Andrew Waterman <andrew at sifive dot com> changed:

           What    |Removed                     |Added
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                 CC|                            |andrew at sifive dot com

--- Comment #2 from Andrew Waterman <andrew at sifive dot com> ---
The vector reduction instructions have their own more relaxed overlap
constraint that overrides the generic text.  "The destination vector register
can overlap the source operands, including the mask register."  I think this
code is OK.