[Bug target/124736] New: RISCV: backend generates an invalid vwredsum.vs insn with overlapping register operands

[bergner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124736

            Bug ID: 124736
           Summary: RISCV: backend generates an invalid vwredsum.vs insn
                    with overlapping register operands
           Product: gcc
           Version: 16.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: bergner at gcc dot gnu.org
  Target Milestone: ---

The following test case shows the riscv backend generating an illegal vwredsum
insn where the destination register uses the same register as one of the input
registers which is disallowed per the RVV docs: 28.5.2. Vector Operands.

linux$ cat bug.c
int a, b;
short *c;
void
foo (void)
{
  for (; b; )
    ;
  for (; b < 16; b++)
    a += c[b];
}
linux$ gcc -S -O2 -march=rv64gv_zvl256b -mrvv-max-lmul=conv-dynamic bug.c
linux$ cat bug.s
[snip]
foo:
.LFB0:
        .cfi_startproc
        lui     a3,%hi(b)
        lw      a5,%lo(b)(a3)
        bne     a5,zero,.L3
        lui     a2,%hi(c)
        vsetivli        zero,16,e32,m2,ta,ma
        lui     a4,%hi(a)
        li      a0,16
        ld      a1,%lo(c)(a2)
        vmv.s.x v2,zero
        lw      a2,%lo(a)(a4)
        sw      a0,%lo(b)(a3)
        vle16.v v1,0(a1)
        vsetvli zero,zero,e16,m1,ta,ma
        vwredsum.vs     v1,v1,v2              <- Illegal operand usage
        vsetivli        zero,0,e32,m1,ta,ma
        vmv.x.s a5,v1
        addw    a5,a5,a2
        sw      a5,%lo(a)(a4)
        ret
.L3:
        j       .L3