[Bug target/124670] bpf: Fix bogosity in zero_extendsidi2 for reg -> reg

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124670

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Vineet Gupta <vineetg@gcc.gnu.org>:

https://gcc.gnu.org/g:bd275e81812cbc010a87ebc3413236510c7f57d3

commit r16-8312-gbd275e81812cbc010a87ebc3413236510c7f57d3
Author: Vineet Gupta <vineet.gupta@linux.dev>
Date:   Thu Mar 26 11:01:24 2026 -0700

    bpf: md: fix zero_extendsidi2 reg->reg codegen [PR124670]

    Currently the following RTL for zero extension

    | (insn 8 7 9 (set (reg:DI 0 %r0 [25])
    |        (zero_extend:DI (reg:SI 0 %r0 [24])))  {zero_extendsidi2}
    |     (nil))

    generates

    |   r0 = r0

    which is just a 64-bit copy and doesn't clear the upper 32-bits as
    semantically required by the pattern.

    The issue is pattern's asm template missing âwâ/'W' causing
bpf_print_register ()
    to only emit 'r' regs. Using âWâ in template generates correct code.

    |   w0 = w0

    Note that 'W specifier ignores the RTL mode and unconditionally emits
    the 'w' reg which might feel like creating a potential future bug.
    However for this insn, it is correct/completely safe as follows:
     - 'W1' for src operand: src operand has a SI mode in pattern.
     - 'W0' for dst: Technically dst is DI, but the upper 32-bits of output
       have to be 0 due to zero-extension, thus a 'w' reg is OK.

    For selftests this is a wash, except for some spurious changes.

            PR target/124670

    gcc/ChangeLog:

            * config/bpf/bpf.md (zero_extendsidi2): Use 'W' in asm template.

    gcc/testsuite/ChangeLog:

            * gcc.target/bpf/zero-ext.c: New test.

    Signed-off-by: Vineet Gupta <vineet.gupta@linux.dev>