[Bug target/124613] [16 regression] gcc.target/riscv/pr122051.c fails with ICE in emit_move_multi_word since r16-7312-gecc37444062b40

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124613

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:

https://gcc.gnu.org/g:79ef3558c8f4c5a27af2475c5c16506600d50519

commit r16-8302-g79ef3558c8f4c5a27af2475c5c16506600d50519
Author: Robin Dapp <rdapp@oss.qualcomm.com>
Date:   Tue Mar 24 10:58:14 2026 +0100

    RISC-V: Allow all vector modes during builtin registration. [PR124613]

    In r16-7312-gecc37444062b40 we allowed all vector modes for the
    any_target hook.  Since then we would ICE in gcc.target/riscv/pr122051.c
    as emit_move_multi_word would choose a fractional vector mode.

    This patch disallows fractional vector modes for xtheadvector in
    riscv_vector_mode_supported_p but makes an exception for builtin
    registration (through a global variable).  During registration we
    need to have all modes available in order to maintain the registration
    order for LTO streaming.

            PR target/124613

    gcc/ChangeLog:

            * config/riscv/riscv-vector-builtins.cc
(rvv_switcher::rvv_switcher):
            Add riscv_registering_builtins.
            (rvv_switcher::~rvv_switcher): Set riscv_registering_builtins to
            false.
            * config/riscv/riscv.cc (riscv_vector_mode_supported_p): Use
            riscv_registering_builtins.
            * config/riscv/riscv.h: Declare.