[Bug target/106585] RISC-V: Miss optimization with code gen for zbs

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106585

--- Comment #15 from Jeffrey A. Law <law at gcc dot gnu.org> ---
So here's a potential path forward for this BZ.

1. We need to improvce how we find split points.  In particular RISC-V
   would prefer to split at the SIGN_EXTEND rather at the inner arithmetic
   or shifts.  This would be a general improvement, I've seen multiple cases
   where better split points would help.

2. We need to extend ext-dce to convert a SIGN_EXTEND wrapping arithmetic or
   logicals to a SUBREG.  Essentially giving us a way to say we only care
   the low bits in an arithmetic/logical operation.

3. #2 implies that we'll need SUBREG variants of the "w" form operations.

4. We need bset and likely other patterns to generalize to GPR rather than X
   for operand modes.

5. We'll need a bclr variant that handles an embedded SUBREG.


The combination of all of those get us to the desired code generation.