[Bug target/124908] [14/15/16/17 Regression] ICE when folding svld1rq_u8(svptrue_b8(), p) for -msve-vector-bits=128
cvs-commit at gcc dot gnu.org
gcc-bugzilla@gcc.gnu.org
Tue Jun 30 12:43:28 GMT 2026
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124908
--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-15 branch has been updated by Kyrylo Tkachov
<ktkachov@gcc.gnu.org>:
https://gcc.gnu.org/g:fa38f8c2e043ffddaff023174926b0a30f002033
commit r15-11331-gfa38f8c2e043ffddaff023174926b0a30f002033
Author: Kyrylo Tkachov <ktkachov@nvidia.com>
Date: Mon Apr 20 00:56:01 2026 -0700
aarch64: PR124908 Fix ICE in svld1rq fold with -msve-vector-bits=128
svld1rq is a replicated-quadword load: it loads 16 bytes and
replicates them to fill the SVE register. When -msve-vector-bits=128
the instruction can be folded to a normal load.
The GIMPLE fold for svld1rq transforms the intrinsic into a 128-bit
memory load followed by a VEC_PERM_EXPR that replicates the loaded
value. When VL == 128, the VEC_PERM_EXPR becomes an identity
permutation. The checking assertion that validates the permutation
(can_vec_perm_const_p) fails for this degenerate case because the
vec_perm_const hook does not recognise the cross-mode identity
permutation (e.g. V16QI -> VNx16QI).
Fix by detecting when the SVE vector has the same number of elements as
the 128-bit quadword (known_eq (lhs_len, source_nelts)) and emitting a
VIEW_CONVERT_EXPR instead of a VEC_PERM_EXPR.
Bootstrapped and tested on aarch64-none-linux-gnu.
Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>
gcc/ChangeLog:
PR target/124908
* config/aarch64/aarch64-sve-builtins-base.cc
(svld1rq_impl::fold): When the SVE vector length equals the
quadword width, emit VIEW_CONVERT_EXPR instead of VEC_PERM_EXPR.
gcc/testsuite/ChangeLog:
PR target/124908
* gcc.target/aarch64/sve/acle/general/ld1rq_2.c: New test.
(cherry picked from commit b8ac2356c691f76c19246c4c7b94c23015b8b8aa)
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